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| 101 innovation drive san jose, ca 95134 (408) 544-7000 http://www.altera.com stratix device handbook, volume 1 s5v1-3.3
copyright ? 2005 altera corporation. all righ ts reserved. altera, the programmable solu tions company, the stylized altera logo, specific device des- ignations, and all other words and logos that are identified as tr ademarks and/or service marks ar e, unless noted otherwise, th e trademarks and service marks of altera corporation in the u.s. and other countries. all other product or service names are the property of the ir respective holders. al- tera products are protected under numerous u.s. and foreign patents and pending app lications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice . altera assumes no responsibility or liability arising out of t he ap- plication or use of any info rmation, product, or service desc ribed herein except as expressly agreed to in writing by altera corporation. altera customers are advised to obtain the latest ve rsion of device specifications before relying on any published in- formation and before placing orders for products or services . ii altera corporation altera corporation iii contents chapter revision dates .......................................................................... vii about this handb ook .............................................................................. ix how to find information ........................................................................................................ ................ ix how to contact altera .......................................................................................................... ................... ix typographic conventions ........................................................................................................ ................ x section i. stratix de vice family data sheet revision history ............................................................................................................... ............. part i?1 chapter 1. introduction introduction ................................................................................................................... ......................... 1?1 features ....................................................................................................................... ............................ 1?2 chapter 2. stratix architecture functional description ......................................................................................................... ................. 2?1 logic array blocks ............................................................................................................. ................... 2?3 lab interconnects .............................................................................................................. .............. 2?4 lab control signals ............................................................................................................ ............. 2?5 logic elements ................................................................................................................. ...................... 2?6 lut chain & register chain ..................................................................................................... ..... 2?8 addnsub signal ................................................................................................................. ................ 2?8 le operating modes ............................................................................................................. ........... 2?8 clear & preset logic control ................................................................................................... ..... 2?13 multitrack interconnect ........................................................................................................ ............. 2?14 trimatrix memory ............................................................................................................... ................ 2?21 memory modes ................................................................................................................... ............ 2?22 clear signals .................................................................................................................. .................. 2?24 parity bit support ............................................................................................................. .............. 2?24 shift register support ......................................................................................................... ........... 2?25 memory block size .............................................................................................................. ........... 2?26 independent clock mode ......................................................................................................... ..... 2?44 input/output clock mode ........................................................................................................ ... 2?46 read/write clock mode .......................................................................................................... ..... 2?49 single-port mode ............................................................................................................... ............. 2?51 multiplier block ............................................................................................................... ............... 2?57 adder/output blocks ............................................................................................................ ....... 2?61 modes of operation ............................................................................................................. .......... 2?64 iv altera corporation contents stratix device handbook, volume 1 dsp block interface ............................................................................................................ ............ 2?70 plls & clock networks .......................................................................................................... ........... 2?73 global & hierarchical clocking ................................................................................................. .. 2?73 enhanced & fast plls ........................................................................................................... ........ 2?81 enhanced plls .................................................................................................................. ............. 2?87 fast plls ...................................................................................................................... ............ ...... 2?100 i/o structure .................................................................................................................. ........... ......... 2?104 double-data rate i/o pins ...................................................................................................... ... 2?111 external ram interfacing ....................................................................................................... .... 2?115 programmable drive strength ................................................................................................... 2 ?119 open-drain output .............................................................................................................. ........ 2?120 slew-rate control .............................................................................................................. .......... 2?120 bus hold ....................................................................................................................... ........... ...... 2?121 programmable pull-up resistor ................................................................................................ 2? 122 advanced i/o standard support .............................................................................................. 2?12 2 differential on-chip termination ............................... .............................................................. 2? 127 multivolt i/o interface ........................................................................................................ ....... 2?129 high-speed differential i/o support ............................................................................................ 2?130 dedicated circuitry ............................................................................................................ .......... 2?137 byte alignment ................................................................................................................. ............ 2?140 power sequencing & hot socketing ............................................................................................... 2?140 chapter 3. configuration & testing ieee std. 1149.1 (jtag) bounda ry-scan support ........ ........... ........... ........... ........... ......... ......... ...... 3?1 signaltap ii embedded logic analyzer ............................................................................................ 3?5 configuration .................................................................................................................. ....................... 3?5 operating modes ................................................................................................................ .............. 3?5 configuring stratix fpgas with jrunner .................................................................................... 3?7 configuration schemes .......................................................................................................... ......... 3?7 partial reconfiguration ................... ..................................................................................... ............ 3?7 remote update configuration modes .......................... ................................................................ 3?8 stratix automated single event upset (seu) detection ........... ........... ........... ........... ............ ........ 3?12 custom-built circuitry ......................................................................................................... ......... 3?13 software interface ............................................................................................................. .............. 3?13 temperature sensing diode ...................................................................................................... ......... 3?13 chapter 4. dc & switching characteristics operating conditions ........................................................................................................... ................ 4?1 power consumption .............................................................................................................. ............. 4?17 timing model ................................................................................................................... ............ ........ 4?19 preliminary & final timing ..................................................................................................... ..... 4?19 performance .................................................................................................................... ................ 4?20 internal timing parameters ..................................................................................................... ..... 4?22 external timing parameters ..................................................................................................... .... 4?33 stratix external i/o timing .................................................................................................... ...... 4?36 i/o timing measurement methodology .................................................................................... 4?60 external i/o delay parameters ........... ....................................................................................... .. 4?66 altera corporation v contents contents maximum input & output clock rates ...................................................................................... 4?76 high-speed i/o specification ................................................................................................... ........ 4?87 pll specifications ............................................................................................................. ........... ........ 4?94 dll jitter ..................................................................................................................... ........... ............. 4?102 chapter 5. reference & ordering information software ....................................................................................................................... ........................... 5?1 device pin-outs ................................................................................................................ ..................... 5?1 ordering information ........................................................................................................... ................ 5?1 index vi altera corporation contents stratix device handbook, volume 1 altera corporation vii chapter revision dates the chapters in this book, stratix device handbook, volume 1 , were revised on the following dates. where chapters or groups of chapters are av ailable separately, part numbers are listed. chapter 1. introduction revised: july 2005 part number: s51001-3.2 chapter 2. stratix architecture revised: july 2005 part number: s51002-3.2 chapter 3. configuration & testing revised: july 2005 part number: s51003-1.3 chapter 4. dc & switching characteristics revised: july 2005 part number: s51004-3.3 chapter 5. reference & ordering information revised: september 2004 part number: s51005-2.1 viii altera corporation chapter revision dates stratix device handbook, volume 1 altera corporation ix about this handbook this handbook provides comprehe nsive information about the altera ? stratix family of devices. how to find information you can find more information in the following ways: the adobe acrobat find feature, wh ich searches the text of a pdf document. click the binoculars toolba r icon to open the find dialog box. acrobat bookmarks, which serve as an additional table of contents in pdf documents. thumbnail icons, which provide miniature previews of each page, provide a link to the pages. numerous links, shown in green text, which allow you to jump to related information. how to contact altera for the most up-to-date information about altera products, go to the altera world-wide web site at www.altera.com . for technical support on this product, go to www.altera.com/mysupport . for additional information about altera products, consult the sources shown below. information type usa & canada all other locations technical support www.altera.com/mysupport/ www.altera.com/mysupport/ (800) 800-epld (3753) (7:00 a.m. to 5:00 p.m. pacific time) +1 408-544-8767 7:00 a.m. to 5:00 p.m. (gmt -8:00) pacific time product literature www.altera.com www.altera.com altera literature services literature@altera.com literature@altera.com non-technical customer service (800) 767-3753 + 1 408-544-7000 7:00 a.m. to 5:00 p.m. (gmt -8:00) pacific time ftp site ftp.altera.com ftp.altera.com x altera corporation typographic conventions stratix device handbook, volume 1 typographic conventions this document uses the typogr aphic conventions shown below. visual cue meaning bold type with initial capital letters command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. example: save as dialog box. bold type external timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and softw are utility names are shown in bold type. examples: f max , \qdesigns directory, d: drive, chiptrip.gdf file. italic type with initial capital letters document titles are shown in italic ty pe with initial capital letters. example: an 75: high-speed board designs. italic type internal timing parameters and variables are shown in italic type. examples: t pia , n + 1. variable names are enclosed in angle br ackets (< >) and shown in italic type. example: altera corporation section i?1 section i. stratix device family data sheet this section provides the data sheet specifications for stratix ? devices. they contain feature definitions of the internal architecture, configuration and jtag boundary-scan testing information, dc operating conditions, ac timing parameters, a reference to power consumption, and ordering information for stratix devices. this section contains the following chapters: chapter 1, introduction chapter 2, stratix architecture chapter 3, configuration & testing chapter 4, dc & switching characteristics chapter 5, reference & ordering information revision history the table below shows th e revision history for chapters 1 through 5 . chapter date/version changes made 1 july 2005, v3.2 minor content changes. september 2004, v3.1 updated table 1?6 on page 1?5 . april 2004, v3.0 main section page numbers changed on first page. changed pci-x to pci-x 1.0 in ?features? on page 1?2 . global change from signaltap to signaltap ii. the dsp blocks in ?features? on page 1?2 provide dedicated implementation of multipliers that are now ?faster than 300 mhz.? january 2004, v2.2 updated -5 speed grade device information in table 1-6. october 2003, v2.1 add -8 speed grade device information. july 2003, v2.0 format changes throughout chapter. section i?2 altera corporation stratix device family data sheet stratix device handbook, volume 1 2 july 2005 v3.2 added ?clear signals? section. updated ?power sequencing & hot socketing? section. format changes. september 2004, v3.1 updated fast regional clock networks description on page 2?73 . deleted the word preliminary from the ?specification for the maximum time to relock is 100 s? on page 2?90 . added information about differential sstl and hstl outputs in ?external clock outputs? on page 2?92 . updated notes in figure 2?55 on page 2?93 . added information about m counter to ?clock multiplication & division? on page 2?101 . updated note 1 in table 2?58 on page 2?101 . updated description of ?clock multiplication & division? on page 2?88 . updated table 2?22 on page 2?102 . added references to an 349 and an 329 to ?external ram interfacing? on page 2?115 . table 2?25 on page 2?116 : updated the table, updated notes 3 and 4. notes 4, 5, and 6, are now notes 5, 6, and 7, respectively. updated table 2?26 on page 2?117 . added information about pci compliance to page 2?120 . table 2?32 on page 2?126 : updated the table and deleted note 1. updated reference to device pin-outs now being available on the web on page 2?130 . added notes 4 and 5 to table 2?36 on page 2?130 . updated note 3 in table 2?37 on page 2?131 . updated note 5 in table 2?41 on page 2?135 . april 2004, v3.0 added note 3 to rows 11 and 12 in table 2?18 . deleted ?stratix and stratix gx device pll availability? table. added i/o standards row in table 2?28 that support max and min strength. row clk [1,3,8,10] was removed from ta b l e 2 ? 3 0 . added checkmarks in enhanced column for lvpecl, 3.3-v pcml, lvds, and hypertransport technology rows in table 2?32 . removed the left and right i/o banks row in table 2?34 . changed rclk values in figures 2?50 and 2?51 . external ram interfac ing section replaced. november 2003, v2.2 added 672-pin bga package information in table 2?37 . removed support for series and parallel on-chip termination. termination technology renamed diff erential on-chip termination. updated the number of channels per pll in tables 2-38 through 2- 42. updated figures 2?65 and 2?67 . october 2003, v2.1 updated ddr i information. updated table 2?22 . added tables 2?25 , 2?29 , 2?30 , and 2?72 . updated figures 2?59 , 2?65 , and 2?67 . updated the lock detect section. chapter date/version changes made altera corporation section i?3 stratix device family data sheet 2 july 2003, v2.0 added reference on page 2-73 to figures 2-50 and 2-51 for rclk connections. updated ranges for epll post-scale and pre-scale dividers on page 2-85. updated pll reconfiguration frequency from 25 to 22 mhz on page 2-87. new requirement to assert are set signal each pll when it has to re- acquire lock on either a new cloc k after loss of lock (page 2-96). updated max input frequency for clk[1,3,8,10] from 462 to 500, table 2-24. renamed impedance matching to series termination throughout. updated naming convention for dqs pins on page 2-112 to match pin tables. added ddr sdram performance specification on page 2-117. added external reference resistor values for terminator technology (page 2-136). added terminator technology specification on pages 2-137 and 2- 138. updated tables 2-45 to 2-49 to reflect pll cross-bank support for high speed differential c hannels at full speed. wire bond package performance s pecification for ?high? speed channels was increased to 624 mbps from 462 mbps throughout chapter. 3 july 2005, v1.3 updated ?operating modes? section. updated ?temperature sensing diode? section. updated ?ieee std. 1149.1 (jtag) boundary-scan support? section. updated ?configuration? section. january 2005, v1.2 updated limits for jtag chain of devices. september 2004, v1.1 added new section, ?stratix automated single event upset (seu) detection? on page 3?12 . updated description of ?custom-built ci rcuitry? on page 3?13 . april 2003, v1.0 no new changes in stratix device handbook v2.0. 4 july 2005 v3.3 updated tables 4?6 and 4?30 . updated tables 4?103 through 4?108 . updated tables 4?114 through 4?124 . updated table 4?129 . added table 4?130 . chapter date/version changes made section i?4 altera corporation stratix device family data sheet stratix device handbook, volume 1 4 january 2005, 3.2 updated rise and fall input values. september 2004, v3.1 updated note 3 in table 4?8 on page 4?4 . updated table 4?10 on page 4?6 . updated table 4?20 on page 4?12 through table 4?23 on page 4?13 . added rows v il(ac) and v ih(ac) to each table. updated table 4?26 on page 4?14 through table 4?29 on page 4?15 . updated table 4?31 on page 4?16 . updated description of ?external timing parameters? on page 4?33 . updated table 4?36 on page 4?20 . added signals t outco , t xz , and t zx to figure 4?4 on page 4?33 . added rows t m512clkensu and t m512clkenh to table 4?40 on page 4?24 . added rows t m4clkensu and t m4clkenh to table 4?41 on page 4?24 . updated note 2 in table 4?54 on page 4?35 . added rows t mramclkensu and t mramclkenh to table 4?42 on page 4?25 . updated table 4?46 on page 4?29 . updated table 4?47 on page 4?29 . chapter date/version changes made altera corporation section i?5 stratix device family data sheet 4 table 4?48 on page 4?30 : added rows t m512clksensu and t m512clkenh , and updated symbol names. updated power-up current (iccint) required to power a stratix device on page 4?17 . updated table 4?37 on page 4?22 through table 4?43 on page 4?27 . table 4?49 on page 4?31 : added rows t m4kclkensu , t m4kclkenh , t m4kbesu , and t m4kbeh, deleted rows t m4kraddrasu and t m4kraddrh , and updated symbol names. table 4?50 on page 4?31 : added rows t mramclkensu , t mramclkenh , t mrambesu , and t mrambeh , deleted rows t mramaddrasu and t mramraddrh , and updated symbol names. table 4?52 on page 4?34 : updated table, deleted ?conditions? column, and added rows t xz and t zx . table 4?52 on page 4?34 : updated table, deleted ?conditions? column, and added rows t xz and t zx . table 4?53 on page 4?34 : updated table and added rows t xzpll and t zxpll . updated note 2 in table 4?53 on page 4?34 . table 4?54 on page 4?35 : updated table, deleted ?conditions? column, and added rows t xzpll and t zxpll . updated note 2 in table 4?54 on page 4?35 . deleted note 2 from table 4?55 on page 4?36 through table 4?66 on page 4?41 . updated table 4?55 on page 4?36 through table 4?96 on page 4?56 . added rows t xz , t zx , t xzpll , and t zxpll. added note 4 to table 4?101 on page 4?62 . deleted note 1 from table 4?67 on page 4?42 through table 4?84 on page 4?50 . added new section ?i/o timing measurement methodology? on page 4?60 . deleted note 1 from table 4?67 on page 4?42 through table 4?84 on page 4?50 . deleted note 2 from table 4?85 on page 4?51 through table 4?96 on page 4?56 . added note 4 to table 4?101 on page 4?62 . table 4?102 on page 4?64 : updated table and added note 4. updated description of ?external i/o delay parameters? on page 4?66 . added note 1 to table 4?109 on page 4?73 and table 4?110 on page 4?74 . updated table 4?103 on page 4?66 through table 4?110 on page 4?74 . deleted note 2 from table 4?103 on page 4?66 through table 4?106 on page 4?69 . added new paragraph about output adder delays on page 4?68 . updated table 4?110 on page 4?74 . added note 1 to table 4?111 through table 4?113 on page 4?75 . chapter date/version changes made section i?6 altera corporation stratix device family data sheet stratix device handbook, volume 1 4 updated table 4?123 on page 4?85 through table 4?126 on page 4?92 . updated note 3 in table 4?123 on page 4?85 . table 4?125 on page 4?88 : moved to correct order in chapter, and updated table. updated table 4?126 on page 4?92 . updated table 4?127 on page 4?94 . updated table 4?128 on page 4?95 . april 2004, v3.0 table 4?129 on page 4?96 : updated table and added note 10. updated table 4?131 and table 4?132 on page 4?100 . updated table 4?110 on page 4?74 . updated table 4?123 on page 4?85 . updated table 4?124 on page 4?87 . through table 4?126 on page 4?92 . added note 10 to table 4?129 on page 4?96 . moved table 4?127 on page 4?94 to correct order in the chapter. updated table 4?131 on page 4?100 through table 4?132 on page 4?100 . deleted t xz and t zx from figure 4?4 . waveform was added to figure 4?6 . the minimum and maximum duty cycle values in note 3 of table 4?8 were moved to a new ta b l e 4 ? 9 . changes were made to values in sstl-3 class i and ii rows in table 4?17 . note 1 was added to table 4?34 . added t su_r and t su_c rows in table 4?38 . changed table 4?55 title from ?ep1s10 column pin fast regional clock external i/o timing parameters? to ?ep1s10 external i/o timing on column pins using fast regional clock networks.? changed values in tables 4?46 , 4?48 to 4?51 , 4?128 , and 4?131 . added t areset row in tables 4?127 to 4?132 . deleted -5 speed grade column in tables 4?117 to 4?119 and 4?122 to 4?123 . fixed differential waveform in figure 4?1 . added ?definition of i/o skew? section. added t su and t co_c rows and made changes to values in t pre and t clkhl rows in table 4?46 . values changed in the t su and t h rows in table 4?47 . values changed in the t m4kclkhl row in table 4?49 . values changed in the t mramclkhl row in table 4?50 . added ta b l e 4 ? 5 1 to ?internal timing parameters? section. the timing information is preliminary in tables 4?55 through 4?96 . table 4?111 was separated into 3 tables: tables 4?111 to 4?113 . november 2003, v2.2 updated tables 4?127 through 4?129 . chapter date/version changes made altera corporation section i?7 stratix device family data sheet 4 october 2003, v2.1 added -8 speed grade information. updated performance information in table 4?36 . updated timing information in tables 4?55 through 4?96 . updated delay information in tables 4?103 through 4?108 . updated programmable delay information in tables 4?100 and 4?103 . july 2003, v2.0 updated clock rates in tables 4?114 through 4?123 . updated speed grade information in the introduction on page 4-1. corrected figures 4-1 & 4-2 and table 4-9 to reflect how vid and vod are specified. added note 6 to table 4-32. updated stratix performance table 4-35. updated ep1s60 and ep1s80 timing parameters in tables 4-82 to 4- 93. the stratix timing models are final for all devices. updated stratix ioe programmable delay chains in tables 4-100 to 4- 101. added single-ended i/o standard output pin delay adders for loading in table 4-102. added spec for fpll[10..7]clk pins in tables 4-104 and 4-107. updated high-speed i/o specification for j=2 in tables 4-114 and 4- 115. updated epll specification and fast pll specification in tables 4- 116 to 4-120. 5 september 2004, v2.1 updated reference to device pin-outs on page 5?1 to indicate that device pin-outs are no longer incl uded in this manual and are now available on the altera web site. april 2003, v1.0 no new changes in stratix device handbook v2.0. chapter date/version changes made section i?8 altera corporation stratix device family data sheet stratix device handbook, volume 1 altera corporation 1?1 july 2005 1. introduction introduction the stratix ? family of fpgas is based on a 1.5-v, 0.13-m, all-layer copper sram process, with densities of up to 79,040 logic elements (les) and up to 7.5 mbits of ram. stratix devi ces offer up to 22 digital signal processing (dsp) blocks with up to 176 (9-bit 9-bit) embedded multipliers, optimized for dsp applications that enable efficient implementation of high -performance filters an d multipliers. stratix devices support various i/o standards and also offer a complete clock management solution with its hierar chical clock structure with up to 420-mhz performance and up to 12 phase-locked loops (plls). the following shows the main sections in the stratix device family data sheet: section page features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 logic array blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?3 logic elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?6 multitrack interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?14 trimatrix memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?21 digital signal proces sing block . . . . . . . . . . . . . . . . . . . . . . . . 2?52 plls & clock networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?73 i/o structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?104 high-speed differential i/o support. . . . . . . . . . . . . . . . . . 2?130 power sequencing & hot socketing . . . . . . . . . . . . . . . . . . . 2?140 ieee std. 1149.1 (jtag) boundary-s can support. . . . . . . . . . 3?1 signaltap ii embedded logic analyzer . . . . . . . . . . . . . . . . . 3?5 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?5 temperature sensing diode. . . . . . . . . . . . . . . . . . . . . . . . . . . 3?13 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?1 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?17 timing model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?19 software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?1 device pin-outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?1 s51001-3.2 1?2 altera corporation stratix device handbook, volume 1 july 2005 features features the stratix family offers the following features: 10,570 to 79,040 les; see table 1?1 up to 7,427,520 ram bits (928,440 byte s) available without reducing logic resources trimatrix tm memory consisting of three ram block sizes to implement true dual-port memory and first-in first-out (fifo) buffers high-speed dsp blocks provide dedicated implementation of multipliers (faster than 300 mhz), multiply-ac cumulate functions, and finite impulse response (fir) filters up to 16 global clocks with 22 clocking resources per device region up to 12 plls (four enhanced plls and eight fast plls) per device provide spread spectrum, programmable bandwidth, clock switch- over, real-time pll reconfiguratio n, and advanced multiplication and phase shifting support for numerous single-ended and differential i/o standards high-speed differential i/o support on up to 116 channels with up to 80 channels optimized for 840 megabits per second (mbps) support for high-speed networking and communications bus standards including rapidio, ut opia iv, csix, hypertransport tm technology, 10g ethernet xsbi, spi-4 phase 2 (pos-phy level 4), and sfi-4 differential on-chip termination support for lvds support for high-speed external memory, including zero bus turnaround (zbt) sram, quad data rate (qdr and qdrii) sram, double data rate (ddr) sdram, ddr fast cycle ram (fcram), and single data rate (sdr) sdram support for 66-mhz pci (64 and 32 bit) in -6 and faster speed-grade devices, support for 33-mhz pci (64 and 32 bit) in -8 and faster speed-grade devices support for 133-mhz pci-x 1.0 in -5 speed-grade devices support for 100-mhz pci-x 1.0 in -6 and faster speed-grade devices support for 66-mhz pci-x 1.0 in -7 speed-grade devices support for multiple intellectual property megafunctions from altera megacore ? functions and altera megafunction partners program (ampp sm ) megafunctions support for remote configuration updates altera corporation 1?3 july 2005 stratix device handbook, volume 1 introduction table 1?1. stratix device features ? ep1s10, ep1s20, ep1s25, ep1s30 feature ep1s10 ep1s20 ep1s25 ep1s30 les 10,570 18,460 25,660 32,470 m512 ram blocks (32 18 bits) 94 194 224 295 m4k ram blocks (128 36 bits) 60 82 138 171 m-ram blocks (4k 144 bits) 1 2 2 4 total ram bits 920,448 1,669,248 1,944,576 3,317,184 dsp blocks 6 101012 embedded multipliers (1) 48 80 80 96 plls 6 6 6 10 maximum user i/o pins 426 586 706 726 table 1?2. stratix device featur es ? ep1s40, ep1s60, ep1s80 feature ep1s40 ep1s60 ep1s80 les 41,250 57,120 79,040 m512 ram blocks (32 18 bits) 384 574 767 m4k ram blocks (128 36 bits) 183 292 364 m-ram blocks (4k 144 bits) 4 6 9 total ram bits 3,423,744 5,215,104 7,427,520 dsp blocks 14 18 22 embedded multipliers (1) 112 144 176 plls 12 12 12 maximum user i/o pins 822 1,022 1,238 note to ta b l e s 1 ? 1 and 1?2 : (1) this parameter lists the total number of 9 9-bit multipliers for each device. for the total number of 18 18-bit multipliers per device, divide the total number of 9 9-bit multipliers by 2. for the total number of 36 36-bit multipliers per device, divide the total number of 9 9-bit multipliers by 8. 1?4 altera corporation stratix device handbook, volume 1 july 2005 features stratix devices are available in space-saving fineline bga ? and ball-grid array (bga) packages (see tables 1?3 through 1?5 ). all stratix devices support vertical migration within the same package (for example, you can migrate between the ep1s10, ep 1s20, and ep1s25 devices in the 672- pin bga package). vertical migrat ion means that you can migrate to devices whose dedicated pins, configur ation pins, and power pins are the same for a given package across device densities. for i/o pin migration across densities, you must cross-reference the available i/o pins using the device pin-outs for all planned de nsities of a given package type to identify which i/o pins ar e migrational. the quartus ? ii software can automatically cross reference and place all pins except differential pins for migration when given a device migration list. you must use the pin- outs for each device to verify the differential placement migration. a future version of the quartus ii soft ware will support differential pin migration. table 1?3. stratix package options & i/o pin counts device 672-pin bga 956-pin bga 484-pin fineline bga 672-pin fineline bga 780-pin fineline bga 1,020-pin fineline bga 1,508-pin fineline bga ep1s10 345 335 345 426 ep1s20 426 361 426 586 ep1s25 473 473 597 706 ep1s30 683 597 726 ep1s40 683 615 773 822 ep1s60 683 773 1,022 ep1s80 683 773 1,203 note to ta b l e 1 ? 3 : (1) all i/o pin counts include 20 dedicated clock input pins ( clk[15..0]p , clk0n , clk2n , clk9n , and clk11n ) that can be used for data inputs. table 1?4. stratix bga package sizes dimension 672 pin 956 pin pitch (mm) 1.27 1.27 area (mm 2 ) 1,225 1,600 length width (mm mm) 35 35 40 40 altera corporation 1?5 july 2005 stratix device handbook, volume 1 introduction stratix devices are available in up to four speed grades, -5, -6, -7, and -8, with -5 being the fastest. table 1?6 shows stratix device speed-grade offerings. table 1?5. stratix fineli ne bga package sizes dimension 484 pin 672 pin 780 pin 1,020 pin 1,508 pin pitch (mm) 1.00 1.00 1.00 1.00 1.00 area (mm 2 ) 529 729 841 1,089 1,600 length width (mm mm) 23 23 27 27 29 29 33 33 40 40 table 1?6. stratix device speed grades device 672-pin bga 956-pin bga 484-pin fineline bga 672-pin fineline bga 780-pin fineline bga 1,020-pin fineline bga 1,508-pin fineline bga ep1s10 -6, -7 -5, -6, -7 -6, -7 -5, -6, -7 ep1s20 -6, -7 -5, -6, -7 -6, -7 -5, -6, -7 ep1s25 -6, -7 -6, -7, -8 -5, -6, -7 -5, -6, -7 ep1s30 -5, -6, -7 -5, -6, -7, -8 -5, -6, -7 ep1s40 -5, -6, -7 -5, -6, -7, -8 -5, -6, -7 -5, -6, -7 ep1s60 -6, -7 -5, -6, -7 -6, -7 ep1s80 -6, -7 -5, -6, -7 -5, -6, -7 1?6 altera corporation stratix device handbook, volume 1 july 2005 features altera corporation 2?1 july 2005 2. stratix architecture functional description stratix ? devices contain a two-dimensional row- and column-based architecture to implement custom logic. a series of column and row interconnects of varying length and speed provide signal interconnects between logic array bloc ks (labs), memory block structures, and dsp blocks. the logic array consists of labs, wi th 10 logic elements (les) in each lab. an le is a small unit of logic providing efficient implementation of user logic functions. labs are grouped into rows and columns across the device. m512 ram blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). these blocks prov ide dedicated simple dual-port or single-port memory up to 18-bits wide at up to 318 mhz. m512 blocks are grouped into columns across the device in between certain labs. m4k ram blocks are true dual-port me mory blocks with 4k bits plus parity (4,608 bits). these blocks provide dedicated true dual-port, simple dual-port, or single-por t memory up to 36-bits wide at up to 291 mhz. these blocks are grouped into columns across the device in between certain labs. m-ram blocks are true dual-port me mory blocks with 512k bits plus parity (589,824 bits). these blocks provide dedicated true dual-port, simple dual-port, or single-port me mory up to 144-bits wide at up to 269 mhz. several m-ram blocks are located individually or in pairs within the device?s logic array. digital signal processing (dsp) blocks can implem ent up to either eight full-precision 9 9-bit multipliers, four full-precision 18 18-bit multipliers, or one full -precision 36 36-bit mul tiplier with add or subtract features. these blocks also contain 18-bit input shift registers for digital signal processing applications, including fir and infinite impulse response (iir) filters. dsp blocks are grouped into two columns in each device. each stratix device i/o pin is fed by an i/o element (ioe) located at the end of lab rows and columns around the periphery of the device. i/o pins support numerous single-ended and differ ential i/o standards. each ioe contains a bidirectional i/o buffer and six registers for registering input, output, and output -enable signals. when used with s51002-3.2 2?2 altera corporation stratix device handbook, volume 1 july 2005 functional description dedicated clocks, these registers provide exceptional performance and interface support with external memory devi ces such as ddr sdram, fcram, zbt, and qdr sram devices. high-speed serial interface channels support transfers at up to 840 mbps using lvds, lvpecl, 3.3-v pcml, or hypertransport technology i/o standards. figure 2?1 shows an overview of the stratix device. figure 2?1. stratix block diagram m512 ram blocks for dual-port memory, shift registers, & fifo buffers dsp blocks for multiplication and full implementation of fir filters m4k ram blocks for true dual-port memory & other embedded memory functions ioes support ddr, pci, gtl+, sstl-3, sstl-2, hstl, lvds, lvpecl, pcml, hypertransport & other i/o standards ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes labs labs ioes labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs ioes labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs ioes ioes labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs dsp block m-ram block altera corporation 2?3 july 2005 stratix device handbook, volume 1 stratix architecture the number of m512 ram, m4k ram, and dsp blocks varies by device along with row and column numbers and m-ram blocks. table 2?1 lists the resources available in stratix devices. logic array blocks each lab consists of 10 les, le carry chains, lab control signals, local interconnect, lut chain, and register chain connection lines. the local interconnect transfers signals between les in the same lab. lut chain connections transfer the output of one le?s lut to the adjacent le for fast sequential lut connections within the same lab. register chain connections transfer the ou tput of one le?s register to the adjacent le?s register within an lab. the quartus ? ii compiler places associated logic within an lab or adjacent labs, allowing the use of local, lut chain, and register chain connections for performance and area efficiency. figure 2?2 shows the stratix lab. table 2?1. stratix device resources device m512 ram columns/blocks m4k ram columns/blocks m-ram blocks dsp block columns/blocks lab columns lab rows ep1s10 4 / 94 2 / 60 1 2 / 6 40 30 ep1s20 6 / 194 2 / 82 2 2 / 10 52 41 ep1s25 6 / 224 3 / 138 2 2 / 10 62 46 ep1s30 7 / 295 3 / 171 4 2 / 12 67 57 ep1s40 8 / 384 3 / 183 4 2 / 14 77 61 ep1s60 10 / 574 4 / 292 6 2 / 18 90 73 ep1s80 11 / 767 4 / 364 9 2 / 22 101 91 2?4 altera corporation stratix device handbook, volume 1 july 2005 logic array blocks figure 2?2. stratix lab structure lab interconnects the lab local interconnect can drive les within the same lab. the lab local interconnect is driven by column and row interconnects and le outputs within the same lab. ne ighboring labs, m512 ram blocks, m4k ram blocks, or dsp blocks from th e left and right can also drive an lab?s local interconnect through the direct link connection. the direct link connection feature minimi zes the use of row and column interconnects, providing higher performance and flexibility. each le can drive 30 other les through fast local and direct link interconnects. figure 2?3 shows the direct link connection. direct link interconnect from adjacent block direct link interconnect to adjacent block row interconnects of variable speed & length column interconnects of variable speed & length three-sided architecture?local interconnect is driven from either side by columns & labs, & from above by rows local interconnect lab direct link interconnect from adjacent block direct link interconnect to adjacent block altera corporation 2?5 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?3. direct link connection lab control signals each lab contains dedicated logic for driving control signals to its les. the control signals include two clocks, two clock enables, two asynchronous clears, synchronous cl ear, asynchronous preset/load, synchronous load, and add/subtract control signals. this gives a maximum of 10 control signals at a ti me. although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. each lab can use two clocks and two clock enable signals. each lab?s clock and clock enable signals are linked. for exampl e, any le in a particular lab using the labclk1 signal will also use labclkena1 . if the lab uses both the rising and falling edges of a clock, it also uses both lab-wide clock signals. de-asserting th e clock enable signal will turn off the lab-wide clock. each lab can use two asynchronous clear signals and an asynchronous load/preset signal. the as ynchronous load acts as a preset when the asynchronous load data input is tied high. lab direct link interconnect to right direct link interconnect from right lab, trimatrix memory block, dsp block, or ioe output direct link interconnect from left lab, trimatrix memory block, dsp block, or ioe output local interconnect direct link interconnect to left 2?6 altera corporation stratix device handbook, volume 1 july 2005 logic elements with the lab-wide addnsub control signal, a single le can implement a one-bit adder and subtractor. this saves le resources and improves performance for logic functions such as dsp correlators and signed multipliers that alternate between addition and subtraction depending on data. the lab row clocks [7..0] and lab local interconnect generate the lab- wide control signals. the multitrack tm interconnect?s inherent low skew allows clock and control signal di stribution in addition to data. figure 2?4 shows the lab control signal generation circuit. figure 2?4. lab-wide control signals logic elements the smallest unit of logic in the st ratix architecture, the le, is compact and provides advanced feat ures with efficient logic utilization. each le contains a four-input lut, which is a function generator that can implement any function of four variable s. in addition, each le contains a programmable register and carry chain with carry select capability. a single le also supports dynamic single bit addition or subtraction mode selectable by an lab-wide control signal. each le drives all types of interconnects: local, row, column, lut chain, register chain, and direct link interconnects. see figure 2?5 . labclkena1 labclk2 labclk1 labclkena2 asyncload or labpre syncload dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect labclr1 labclr2 synclr addnsub 8 altera corporation 2?7 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?5. stratix le each le?s programmable register can be configured for d, t, jk, or sr operation. each register has data, true asynchronous load data, clock, clock enable, clear, and asynchronous load/preset inputs. global signals, general-purpose i/o pins, or any internal logic can drive the register?s clock and clear control signals. ei ther general-purpose i/o pins or internal logic can drive the clock enable, preset, asynchronous load, and asynchronous data. the asynchronous load data input comes from the data3 input of the le. for combinator ial functions, the register is bypassed and the output of the lut dr ives directly to the outputs of the le. each le has three outputs that drive the local, row, and column routing resources. the lut or register ou tput can drive these three outputs independently. two le outputs drive column or row and direct link routing connections and one drives local interconnect resources. this allows the lut to drive one output while the register drives another output. this feature, called register packing, improves device utilization because the device can use the register and the lut for unrelated labclk1 labclk2 labclr2 labpre/aload carry-in1 carry-in0 lab carry-in clock & clock enable select lab carry-out carry-out1 carry-out0 look-up ta b l e (lut) carry chain row, column, and direct link routing row, column, and direct link routing programmable register prn/ald clrn d q ena register bypass packed register select chip-wide reset labclkena1 labclkena2 synchronous load and clear logic lab-wide synchronous load lab-wide synchronous clear asynchronous clear/preset/ load logic data1 data2 data3 data4 lut chain routing to next le labclr1 local routing register chain output a data addnsub register feedback register chain routing from previous le 2?8 altera corporation stratix device handbook, volume 1 july 2005 logic elements functions. another special packing mo de allows the register output to feed back into the lut of the same le so that the register is packed with its own fan-out lut. this provides another mechanism for improved fitting. the le can also drive out registered and unregistered versions of the lut output. lut chain & register chain in addition to the three general routing outputs, the les within an lab have lut chain and register chain ou tputs. lut chain connections allow luts within the same lab to cascad e together for wide input functions. register chain outputs allow register s within the same lab to cascade together. the register chain output allows an lab to use luts for a single combinatorial function and the register s to be used for an unrelated shift register implementation. these resources speed up connections between labs while saving local in terconnect resources. see ?multitrack interconnect? on page 2?14 for more information on lut chain and register chain connections. addnsub signal the le?s dynamic adder/subtractor feature saves logic resources by using one set of les to implement both an adder and a subtractor. this feature is controlled by the lab-wide control signal addnsub . the addnsub signal sets the lab to perform either a + b or a ? b. the lut computes addition, and subtraction is computed by adding the two?s complement of the intended subtractor . the lab-wide signal converts to two?s complement by inverting the b bits within the lab and setting carry-in = 1 to add one to the least si gnificant bit (lsb). the lsb of an adder/subtractor must be placed in the first le of the lab, where the lab-wide addnsub signal automatic ally sets the carry-in to 1. the quartus ii compiler automatically plac es and uses the adder/subtractor feature when using adder/subtra ctor parameterized functions. le operating modes the stratix le can operate in one of the following modes: normal mode dynamic arithmetic mode each mode uses le resources differently. in each mode, eight available inputs to the le?the four data inputs from the lab local interconnect; carry-in0 and carry-in1 from the previous le; the lab carry-in from the previous carry-chain lab; and the register chain connection? are directed to different destinatio ns to implement the desired logic function. lab-wide signals provid e clock, asynchronous clear, altera corporation 2?9 july 2005 stratix device handbook, volume 1 stratix architecture asynchronous preset lo ad, synchronous clear, synchronous load, and clock enable control for the register. these lab-wide signals are available in all le modes. the addnsub control signal is allowed in arithmetic mode. the quartus ii software, in conjunct ion with parameterized functions such as library of parameterized mo dules (lpm) function s, automatically chooses the appropriate mode for co mmon functions such as counters, adders, subtractors, and arithmetic functions. if required, you can also create special-purpose functions that specify which le operating mode to use for optimal performance. normal mode the normal mode is suitable for general logic applications and combinatorial functions. in normal mo de, four data inputs from the lab local interconnect are inputs to a four-input lut (see figure 2?6 ). the quartus ii compiler automaticall y selects the carry-in or the data3 signal as one of the inputs to th e lut. each le can use lut chain connections to drive its combinatorial ou tput directly to the next le in the lab. asynchronous load data fo r the register comes from the data3 input of the le. les in normal mode support packed registers. figure 2?6. le in normal mode note to figure 2?6 : (1) this signal is only allowed in normal mode if the le is at the end of an adder/subtractor chain. data1 4-input lut data2 data3 cin (from cout of previous le) data4 addnsub (lab wide) clock (lab wide) ena (lab wide) aclr (lab wide) aload (lab wide) ald/pre clrn d q ena a data sclear (lab wide) sload (lab wide) register chain connection lut chain connection register chain output row, column, and direct link routing row, column, and direct link routing local routing register feedback (1) 2?10 altera corporation stratix device handbook, volume 1 july 2005 logic elements dynamic arithmetic mode the dynamic arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. an le in dynamic arithmetic mode uses four 2-input luts configurable as a dynamic adder/subtractor. the first two 2-input luts compute two summations based on a possible carry-in of 1 or 0; the other two luts generate carry outputs for the two chains of the ca rry select circuitry. as shown in figure 2?7 , the lab carry-in signal selects either the carry-in0 or carry-in1 chain. the selected chain?s logic level in turn determines which parallel sum is generated as a combinatorial or registered output. for example, when implementing an adder, the sum output is the selection of two possible calculated sums: data1 + data2 + carry-in0 or data1 + data2 + carry-in1 . the other two luts use the data1 and data2 signals to generate two possible carry-out signals?one for a carry of 1 and the other for a carry of 0. the carry-in0 signal acts as the carry select for the carry-out0 output and carry-in1 acts as the carry select for the carry-out1 output. les in arithmetic mode can drive out registered and unregistered versions of the lut output. the dynamic arithmetic mode also of fers clock enable, counter enable, synchronous up/down control, sync hronous clear, sy nchronous load, and dynamic adder/subtrac tor options. the lab local interconnect data inputs generate the counter enable and synchronous up/down control signals. the synchronous clear and synchronous load options are lab- wide signals that affect all registers in the lab. the quartus ii software automatically places any registers that are not used by the counter into other labs. the addnsub lab-wide signal controls whether the le acts as an adder or subtractor. altera corporation 2?11 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?7. le in dynamic arithmetic mode note to figure 2?7 : (1) the addnsub signal is tied to the carry input for the first le of a carry chain only. carry-select chain the carry-select chain provides a very fast carry-select function between les in arithmetic mode. the carry-sel ect chain uses th e redundant carry calculation to increase the speed of ca rry functions. the le is configured to calculate outputs for a possible carry-in of 1 and carry-in of 0 in parallel. the carry-in0 and carry-in1 signals from a lower-order bit feed forward into the higher-order bit via the parallel carry chain and feed into both the lut and the next port ion of the carry chain. carry-select chains can begin in any le within an lab. the speed advantage of the carry-select chain is in the parallel pre- computation of carry chains. si nce the lab carry-in selects the precomputed carry ch ain, not every le is in th e critical path. only the propagation delay between lab carry-in generation (le 5 and le 10) are now part of the critical path. this feature allows the stratix architecture to implement high-speed counters, adders , multipliers, pa rity functions, and comparators of arbitrary width. data1 lut data2 data3 addnsub (lab wide) clock (lab wide) ena (lab wide) aclr (lab wide) ald/pre clrn d q ena a data register chain connection lut lut lut carry-out1 carry-out0 lab carry-in carry-in0 carry-in1 (1) sclear (lab wide) sload (lab wide) lut chain connection register chain output row, column, and direct link routing row, column, and direct link routing local routing aload (lab wide) register feedback 2?12 altera corporation stratix device handbook, volume 1 july 2005 logic elements figure 2?8 shows the carry-select circuitry in an lab for a 10-bit full adder. one portion of the lut generates the sum of two bits using the input signals and the appr opriate carry-in bit; the sum is routed to the output of the le. the register can be bypassed for simple adders or used for accumulator functions. another portion of the lut generates carry- out bits. an lab-wide carry in bit selects which chain is used for the addition of given inputs. the ca rry-in signal for each chain, carry-in0 or carry-in1 , selects the carry-out to carry forward to the carry-in signal of the next-higher-order bit. th e final carry-out signal is routed to an le, where it is fed to local, row, or column interconnects. the quartus ii compiler automatically creates carry chain logic during design processing, or you can create it manually during design entry. parameterized functions such as lpm functions autom atically take advantage of carry chains for the appropriate functions. the quartus ii compiler creates carr y chains longer than 10 les by linking labs together automatically. for enhanced fitting, a long carry chain runs vertically a llowing fast horizontal connections to trimatrix ? memory and dsp blocks. a carry chai n can continue as far as a full column. altera corporation 2?13 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?8. carry select chain clear & preset logic control lab-wide signals control the logic for the register?s clear and preset signals. the le directly supports an asynchronous clear and preset function. the register preset is achi eved through the asynchronous load of a logic high. the direct asynchro nous preset does not require a not- gate push-back technique. stratix devices support simultaneous preset/ le4 le3 le2 le1 a1 b1 a2 b2 a3 b3 a4 b4 sum1 sum2 sum3 sum4 le10 le9 le8 le7 a7 b7 a8 b8 a9 b9 a10 b10 sum7 le6 a6 b6 sum6 le5 a5 b5 sum5 sum8 sum9 sum10 01 01 lab carry-in lab carry-out lut lut lut lut data1 lab carry-in data2 carry-in0 carry-in1 carry-out0 carry-out1 sum 2?14 altera corporation stratix device handbook, volume 1 july 2005 multitrack interconnect asynchronous load, and clear signals. an asynchronous clear signal takes precedence if both signals are as serted simultaneously. each lab supports up to two clears and one preset signal. in addition to the clear and preset ports, stratix devices provide a chip- wide reset pin ( dev_clrn ) that resets all registers in the device. an option set before compilation in the qu artus ii software controls this pin. this chip-wide reset overrides all other control signals. multitrack interconnect in the stratix architecture, connecti ons between les, trimatrix memory, dsp blocks, and device i/o pins are provided by the multitrack interconnect structur e with directdrive tm technology. the multitrack interconnect consists of continuous , performance-optimi zed routing lines of different lengths and speeds used for inter- and intra-design block connectivity. the quartus ii compiler au tomatically places critical design paths on faster interconnects to improve design performance. directdrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement within the device. the multitrack interconnect and directdrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycl es that typically follow design changes and additions. the multitrack interconnect consists of row and column interconnects that span fixed distances. a routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities. dedicated row interconnects route signals to and from labs, dsp blocks, and trimatrix memory within the same row. these row resources include: direct link interconnects between labs and adjacent blocks. r4 interconnects traversing four blocks to the right or left. r8 interconnects traversing eigh t blocks to the right or left. r24 row interconnects for high-speed access across the length of the device. the direct link interconnect allows an lab, dsp block, or trimatrix memory block to drive into the local in terconnect of its left and right neighbors and then back into itself . only one side of a m-ram block interfaces with direct link and row interconnects. this provides fast communication between adjacent labs and/or blocks without using row interconnect resources. the r4 interconnects span four labs, three labs and one m512 ram block, two labs and one m4k ram block, or two labs and one dsp block to the right or left of a source lab. these resources are used for fast altera corporation 2?15 july 2005 stratix device handbook, volume 1 stratix architecture row connections in a four-lab region . every lab has its own set of r4 interconnects to drive either left or right. figure 2?9 shows r4 interconnect connections from an lab. r4 interconnects can drive and be driven by dsp blocks and ram blocks and horizontal ioes. for lab interfacing, a primary lab or lab neighbor can drive a given r4 interconnect. for r4 interconnects th at drive to the right, the primary lab and right neighbor can drive on to the interconnect. for r4 interconnects that drive to the left, the primary lab and its left neighbor can drive on to the interconnect. r4 interconnects can drive other r4 interconnects to extend the range of labs they can drive. r4 interconnects can also drive c4 an d c16 interconnects for connections from one row to another. additional ly, r4 interconnects can drive r24 interconnects. figure 2?9. r4 interconnect connections notes to figure 2?9 : (1) c4 interconnects can drive r4 interconnects. (2) this pattern is repeated for every lab in the lab row. the r8 interconnects span eight la bs, m512 or m4k ram blocks, or dsp blocks to the right or left from a sour ce lab. these resources are used for fast row connections in an eight-lab region. every lab has its own set of r8 interconnects to drive either left or right. r8 interconnect connections between labs in a row are similar to the r4 connections shown in figure 2?9 , with the exception that they connect to eight labs to the right or left, not four. like r4 interconnects, r8 interconnects can drive and be driven by all types of architecture blocks. r8 interconnects primary lab (2) r4 interconnect driving left adjacent lab can drive onto another lab's r4 interconnect c4, c8, and c16 column interconnects (1) r4 interconnect driving right lab neighbor lab neighbor 2?16 altera corporation stratix device handbook, volume 1 july 2005 multitrack interconnect can drive other r8 interconnects to ex tend their range as well as c8 interconnects for row-to-row connections. one r8 interconnect is faster than two r4 interconnects connected together. r24 row interconnects span 24 labs and provide the fastest resource for long row connections between labs, trimatrix memory, dsp blocks, and ioes. the r24 row interconnects can cross m-ram blocks. r24 row interconnects drive to other row or column interconnects at every fourth lab and do not drive directly to lab local interconnects. r24 row interconnects drive lab local interconnects via r4 and c4 interconnects. r24 interconnects can drive r24, r4, c16, and c4 interconnects. the column interconnect operates si milarly to the row interconnect and vertically routes signals to and from labs, trimatrix memory, dsp blocks, and ioes. each column of labs is served by a dedicated column interconnect, which vertically routes signals to and from labs, trimatrix memory and dsp blocks, and horizontal ioes. these column resources include: lut chain interconne cts within an lab register chain intercon nects within an lab c4 interconnects traversing a distance of four blocks in up and down direction c8 interconnects traversing a dist ance of eight blocks in up and down direction c16 column interconnects for high -speed vertical routing through the device stratix devices include an enhanced interconnect structure within labs for routing le output to le input connections faster using lut chain connections and register chain conne ctions. the lut chain connection allows the combinatorial output of an le to directly drive the fast input of the le right below it, bypassing the local interconnect. these resources can be used as a high-speed connecti on for wide fan-in functions from le 1 to le 10 in the same lab. the register chain connection allows the register output of one le to connect directly to the register input of the next le in the lab for fast shift registers. the quartus ii compiler automatically takes advantage of th ese resources to improve utilization and performance. figure 2?10 shows the lut chain and register chain interconnects. altera corporation 2?17 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?10. lut chain & register chain interconnects the c4 interconnects span four labs , m512, or m4k blocks up or down from a source lab. every lab has its own set of c4 interconnects to drive either up or down. figure 2?11 shows the c4 interconnect connections from an lab in a column. the c4 interconnects can drive and be driven by all types of architecture bloc ks, including dsp blocks, trimatrix memory blocks, and vertical ioes. for lab interconnection, a primary lab or its lab neighbor can drive a given c4 interconnect. c4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. le 1 le 2 le 3 le 4 le 5 le 6 le 7 le 8 le 9 le 10 lut chain routing to adjacent le local interconnect register chain routing to adjacen t le's register input local interconnect routing among les in the lab 2?18 altera corporation stratix device handbook, volume 1 july 2005 multitrack interconnect figure 2?11. c4 interc onnect connections note (1) note to figure 2?11 : (1) each c4 interconnect can drive either up or down four rows. c4 interconnect drives local and r 4 interconnects up to four rows adjacent lab can drive onto neighboring lab's c4 interconnect c4 interconnect driving up c4 interconnect driving down lab row interconnect local interconnect altera corporation 2?19 july 2005 stratix device handbook, volume 1 stratix architecture c8 interconnects span eight labs, m512, or m4k blocks up or down from a source lab. every lab has its own set of c8 interconnects to drive either up or down. c8 interconnect connections between the labs in a column are similar to the c4 connections shown in figure 2?11 with the exception that they connect to eigh t labs above and below. the c8 interconnects can drive and be driven by all types of architecture blocks similar to c4 interconnects. c8 interconnects can drive each other to extend their range as well as r8 interconnects for column-to-column connections. c8 interconnects are fa ster than two c4 interconnects. c16 column interconnects span a length of 16 labs and provide the fastest resource for long column connections between labs, trimatrix memory blocks, dsp blocks, and ioes. c16 interconnects can cross m- ram blocks and also drive to row and column interconnects at every fourth lab. c16 interconnects drive lab local interconnects via c4 and r4 interconnects and do not drive lab local interconnects directly. all embedded blocks communicate with the logic array similar to lab- to-lab interfaces. each block (i.e., trimatrix memory and dsp blocks) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. these blocks also have direct link interconnects for fast co nnections to and from a neighboring lab. all blocks are fed by the row lab clocks, labclk[7..0] . 2?20 altera corporation stratix device handbook, volume 1 july 2005 multitrack interconnect table 2?2 shows the stratix device?s routing scheme. table 2?2. stratix devi ce routing scheme source destination lut chain register chain local interconnect direct link interconnect r4 interconnect r8 interconnect r24 interconnect c4 interconnect c8 interconnect c16 interconnect le m512 ram block m4k ram block m-ram block dsp blocks column ioe row ioe lut chain v register chain v local interconnect vvvvvvv direct link interconnect v r4 interconnect vvvvv r8 interconnect vvv r24 interconnect vvvv c4 interconnect vv v c8 interconnect vvv c16 interconnect vvvv le vvvvvv vv m512 ram block vvvv vv m4k ram block vvvv vv m-ram block vv dsp blocks vvvv vv column ioe vvvv row ioe v vvvvv altera corporation 2?21 july 2005 stratix device handbook, volume 1 stratix architecture trimatrix memory trimatrix memory consists of three types of ram blocks: m512, m4k, and m-ram blocks. although these me mory blocks are different, they can all implement various types of memory with or without parity, including true dual-port, simple du al-port, and single-port ram, rom, and fifo buffers. table 2?3 shows the size and features of the different ram blocks. table 2?3. trimatrix memory features (part 1 of 2) memory feature m512 ram block (32 18 bits) m4k ram block (12836bits) m-ram block (4k 144 bits) maximum performance (1) (1) (1) true dual-port memory vv simple dual-port memory vvv single-port memory vvv shift register vv rom vv (2) fifo buffer vvv byte enable vv parity bits vvv mixed clock mode vvv memory initialization vv simple dual-port memory mixed width support vvv true dual-port memory mixed width support vv power-up conditions outputs cl eared outputs cleared outputs unknown register clears input and output registers input and output registers output registers mixed-port read- during-write unknown output/old data unknown output/old data unknown output 2?22 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory 1 violating the setup or hold time on the address registers could corrupt the memory contents. this applies to both read and write operations. memory modes trimatrix memory blocks include inpu t registers that synchronize writes and output registers to pipeline designs and improve system performance. m4k and m-ram memory blocks offer a true dual-port mode to support any combination of two-port operations: two reads, two writes, or one read and one write at two different clock frequencies. figure 2?12 shows true dual-port memory. figure 2?12. true dual-port memory configuration configurations 512 1 256 2 128 4 64 8 64 9 32 16 32 18 4k 1 2k 2 1k 4 512 8 512 9 256 16 256 18 128 32 128 36 64k 8 64k 9 32k 16 32k 18 16k 32 16k 36 8k 64 8k 72 4k 128 4k 144 notes to ta b l e 2 ? 3 : (1) see table 4?36 for maximum performance information. (2) the m-ram block does not support memory initializations. however, the m-ram block can emulate a rom function using a dual-port ram bock. the stratix device must write to the dual-port memory once and then disable the write-enable ports afterwards. table 2?3. trimatrix memory features (part 2 of 2) memory feature m512 ram block (32 18 bits) m4k ram block (12836bits) m-ram block (4k 144 bits) data a [ ] address a [ ] wren a clock a clocken a q a [ ] aclr a data b [ ] address b [ ] wren b clock b clocken b q b [ ] aclr b ab altera corporation 2?23 july 2005 stratix device handbook, volume 1 stratix architecture in addition to true dual-port memory , the memory blocks support simple dual-port and single-por t ram. simple dual-port memory supports a simultaneous read and write and can ei ther read old data before the write occurs or just read the don?t care bits. single-port me mory supports non- simultaneous reads and writes, but the q[] port will output the data once it has been written to the memory (if the outputs are not registered) or after the next rising edge of the clock (if the outputs are registered). for more information, see chapter 2, trimatrix embedded memory blocks in stratix & stratix gx devices of the stratix device handbook, volume 2 . figure 2?13 shows these different ram memory port configurations for trimatrix memory. figure 2?13. simple dual-port & singl e-port memory configurations note to figure 2?13 : (1) two single-port memory blocks can be implemented in a single m4k block as long as each of the two independent block sizes is equal to or less than half of the m4k block size. the memory blocks also enable mixed-width data ports for reading and writing to the ram ports in dual-por t ram configuration. for example, the memory block can be wr itten in 1 mode at port a and read out in 16 mode from port b. data[ ] wraddress[ ] wren inclock inclocken inaclr rdaddress[ ] rden q[ ] outclock outclocken outaclr data[ ] address[ ] wren inclock inclocken inaclr q[ ] outclock outclocken outaclr single-port memory (1) simple dual-port memory 2?24 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory trimatrix memory architecture can implement pipelined ram by registering both the input and outp ut signals to the ram block. all trimatrix memory block inputs are registered providing synchronous write cycles. in synchronous operatio n, the memory block generates its own self-timed strobe write enable ( wren ) signal derived from the global or regional clock. in contrast, a circuit using asynchronous ram must generate the ram wren signal while ensuring its data and address signals meet setup and hold time specifications relative to the wren signal. the output registers can be bypassed. flow-through reading is possible in the simple dual-port mo de of m512 and m4k ram blocks by clocking the read enable and read ad dress registers on the negative clock edge and bypassing the output registers. two single-port memory blocks can be implemented in a single m4k block as long as each of the two indepe ndent block sizes is equal to or less than half of the m4k block size. the quartus ii software automatically implements larger memory by combining multiple trimatrix memory blocks. for example, two 256 16-bit ram blocks can be co mbined to form a 256 32-bit ram block. memory performance does n ot degrade for memory blocks using the maximum number of words availa ble in one memory block. logical memory blocks using less than the maximum number of words use physical blocks in parallel, eliminating any external control logic that would increase delays. to create a la rger high-speed memory block, the quartus ii software automatically co mbines memory blocks with le control logic. clear signals when applied to input registers, the asynchronous clear signal for the trimatrix embedded memory immediately clears the input registers. however, the output of the memory block does not show the effects until the next clock edge. when applied to output registers, the asynchronous clear signal clears the output registers and the effects are seen immediately. parity bit support the memory blocks support a parity bit for each byte. the parity bit, along with internal le logic, can implement parity checking for error detection to ensure data integrity. you can also use parity-size data words to store user-specified control bits . in the m4k and m-ram blocks, byte enables are also available for data in put masking during write operations. altera corporation 2?25 july 2005 stratix device handbook, volume 1 stratix architecture shift register support you can configure embedded memory blocks to implement shift registers for dsp applications such as pseudo-random number generators, multi- channel filtering, auto-correlation, and cross-correlation functions. these and other dsp applications require local data storage, traditionally implemented with standard flip-flops, which can quickly consume many logic cells and routing resources for la rge shift registers. a more efficient alternative is to use embedded memory as a shift register block, which saves logic cell and routing resources and provides a more efficient implementation with th e dedicated circuitry. the size of a w m n shift register is determined by the input data width ( w ), the length of the taps ( m ), and the number of taps ( n ). the size of a w m n shift register must be less than or equal to the maximum number of memory bits in the resp ective block: 576 bits for the m512 ram block and 4,608 bits for the m4 k ram block. the total number of shift register outputs (number of taps n width w ) must be less than the maximum data width of the ram bl ock (18 for m512 blocks, 36 for m4k blocks). to create larger shift regist ers, the memory blocks are cascaded together. data is written into each address locati on at the falling edge of the clock and read from the address at the rising edge of the clock. the shift register mode logic automatically controls the positive and negative edge clocking to shift the data in one clock cycle. figure 2?14 shows the trimatrix memory block in the shift register mode. 2?26 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory figure 2?14. shift register memory configuration memory block size trimatrix memory provides three different memory sizes for efficient application support. the large number of m512 blocks are ideal for designs with many shallow first-in fi rst-out (fifo) buffers. m4k blocks provide additional resources for ch annelized functions that do not require large amounts of storage. the m-ram blocks provide a large single block of ram ideal for data packet storage. the different-sized blocks allow stratix devices to effici ently support variable-sized memory in designs. the quartus ii software automatical ly partitions the user-defined memory into the embedded memory bloc ks using the most efficient size combinations. you can also manually assign the memory to a specific block size or a mixture of block sizes. m -bit shift register w w m -bit shift register m -bit shift register m -bit shift register w w w w w w w m n shift register n numbe r of taps altera corporation 2?27 july 2005 stratix device handbook, volume 1 stratix architecture m512 ram block the m512 ram block is a simple dual-port memory block and is useful for implementing small fifo buffers, dsp, and clock domain transfer applications. each block contains 576 ram bits (including parity bits). m512 ram blocks can be configured in the following modes: simple dual-port ram single-port ram fifo rom shift register when configured as ram or rom, you can use an initialization file to pre-load the memory contents. the memory address depths and outp ut widths can be configured as 512 1, 256 2, 128 4, 64 8 (64 9 bits with parity), and 32 16 (32 18 bits with parity). mixed-widt h configurations are also possible, allowing different read and write widths. table 2?4 summarizes the possible m512 ram block configurations. when the m512 ram block is configured as a shift register block, a shift register of size up to 576 bits is possible. the m512 ram block can also be configured to support serializer and deserializer applications. by using the mixed-width support in combination with ddr i/o standards, the block can function as a serdes to support low-speed serial i/o standards using global or regional clocks. see ?i/o structure? on page 2?104 for details on dedicated serdes in stratix devices. table 2?4. m512 ram block configur ations (simple dual-port ram) read port write port 512 1 256 2 128 4 64 8 32 16 64 9 32 18 512 1 v v vvv 256 2 v v vvv 128 4 vvv v 64 8 vv v 32 16 vvv v 64 9 v 32 18 v 2?28 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory m512 ram blocks can have different cl ocks on its inputs and outputs. the wren , datain , and write address registers are all clocked together from one of the two cl ocks feeding the block. the read address, rden , and output registers can be clocked by ei ther of the two cl ocks driving the block. this allows the ram block to operate in read/write or input/output clock modes. only the ou tput register can be bypassed. the eight labclk signals or local interconnect can drive the inclock , outclock , wren , rden , inclr , and outclr signals. because of the advanced interconnect between th e lab and m512 ram blocks, les can also control the wren and rden signals and the ram clock, clock enable, and asynchronous clear signals. figure 2?15 shows the m512 ram block control signal generation logic. the ram blocks within st ratix devices have local interconnects to allow les and interconnects to drive into ram blocks. the m512 ram block local interconnect is driven by the r4, r8, c4, c8, and direct link interconnects from adjacent labs. the m512 ram blocks can communicate with labs on either the left or righ t side through these row interconnects or with lab columns on the left or right side with the column interconnects. up to 10 direct link input connections to the m512 ram block are possible from the left adjacent labs and another 10 possible from the right adjacent lab. m512 ram outputs can also connect to left and right labs throug h 10 direct link interconnects. the m512 ram block has equal opportunity for access and performance to and from labs on either its left or right side. figure 2?16 shows the m512 ram block to logic array interface. altera corporation 2?29 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?15. m512 ram block control signals inclocken outclock inclock outclocken rden wren dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect inclr outclr 8 local interconnect local interconnect 2?30 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory figure 2?16. m512 ram block lab row interface m4k ram blocks the m4k ram block includes support for true dual-port ram. the m4k ram block is used to implement buffer s for a wide variety of applications such as storing processor code, im plementing lookup schemes, and implementing larger memory applications. each block contains 4,608 ram bits (including parity bits). m4k ram blocks can be configured in the following modes: true dual-port ram simple dual-port ram single-port ram fifo rom shift register when configured as ram or rom, you can use an initialization file to pre-load the memory contents. dataout m512 ram block datain clocks 10 direct link interconnect from adjacent lab direct link interconnect to adjacent lab direct link interconnect from adjacent lab direct link interconnect to adjacent lab small ram block local interconnect region c4 and c8 interconnects r4 and r8 interconnects control signals address lab row clocks 2 8 altera corporation 2?31 july 2005 stratix device handbook, volume 1 stratix architecture the memory address depths and outp ut widths can be configured as 4,096 1, 2,048 2, 1,024 4, 512 8 (or 512 9 bits), 256 16 (or 256 18 bits), and 128 32 (or 128 36 bits). the 128 32- or 36-bit configuration is not available in the true dual-port mode. mixed-width configurations are also possible, allowing different read and write widths. tables 2?5 and 2?6 summarize the possible m4k ram block configurations. when the m4k ram block is configured as a shift register block, you can create a shift register up to 4,608 bits ( w m n ). table 2?5. m4k ram block confi gurations (simple dual-port) read port write port 4k 12k 21k 4 512 8 256 16 128 32 512 9 256 18 128 36 4k 1 vvvv v v 2k 2 vvvv v v 1k 4 vvvv v v 512 8 vvvv v v 256 16 vvvv v v 128 32 vvvv v v 512 9 vv v 256 18 vv v 128 36 vv v table 2?6. m4k ram block confi gurations (true dual-port) port a port b 4k 12k 21k 4 512 8 256 16 512 9 256 18 4k 1 vvvvv 2k 2 vvvvv 1k 4 vvvvv 512 8 vvvvv 256 16 vvvvv 512 9 vv 256 18 vv 2?32 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory m4k ram blocks support byte writes when the write port has a data width of 16, 18, 32, or 36 bits. the byte enables al low the input data to be masked so the device can write to specific bytes. the unwritten bytes retain the previous written value. table 2?7 summarizes the byte selection. the m4k ram blocks allow for differ ent clocks on their inputs and outputs. either of the two clocks feeding the block can clock m4k ram block registers ( renwe , address, byte enable, datain , and output registers). only the output register can be bypassed. the eight labclk signals or local interconnects can drive the control signals for the a and b ports of the m4k ram block. les can also control the clock_a , clock_b , renwe_a , renwe_b , clr_a , clr_b , clocken_a , and clocken_b signals, as shown in figure 2?17 . the r4, r8, c4, c8, and direct link interconnects from adjacent labs drive the m4k ram block local inte rconnect. the m4k ram blocks can communicate with labs on either the left or righ t side through these row resources or with lab columns on either the right or left with the column resources. up to 10 direct link inpu t connections to the m4k ram block are possible from the left adjacent labs and another 10 possible from the right adjacent lab. m4k ram block outputs can also connect to left and right labs through 10 direct link interconnects each. figure 2?18 shows the m4k ram block to logic array interface. table 2?7. byte enable for m4k blocks notes (1) , (2) byteena[3..0] datain 18 datain 36 [0] = 1 [8..0] [8..0] [1] = 1 [17..9] [17..9] [2] = 1 ? [26..18] [3] = 1 ? [35..27] notes to ta b l e 2 ? 7 : (1) any combination of byte enables is possible. (2) byte enables can be used in the sa me manner with 8-bit words, i.e., in 16 and 32 modes. altera corporation 2?33 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?17. m4k ram bl ock control signals figure 2?18. m4k ram block lab row interface clocken_a renwe_a clock_a alcr_a alcr_b renwe_b dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect clocken_b clock_b 8 local interconnect local interconnect local interconnect local interconnect local interconnect dataout m4k ram block datain address 10 direct link interconnect from adjacent lab direct link interconnect to adjacent lab direct link interconnect from adjacent lab direct link interconnect to adjacent lab m4k ram block local interconnect region c4 and c8 interconnects r4 and r8 interconnects lab row clocks clocks byte enable control signals 8 2?34 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory m-ram block the largest trimatrix memory block, the m-ram block, is useful for applications where a large volume of data must be stored on-chip. each block contains 589,824 ram bits (inc luding parity bits). the m-ram block can be configured in the following modes: true dual-port ram simple dual-port ram single-port ram fifo ram you cannot use an initialization file to initialize the contents of a m-ram block. all m-ram block contents powe r up to an undefined value. only synchronous operation is supported in the m-ram block, so all inputs are registered. output registers ca n be bypassed. the memory address and output width can be configured as 64k 8 (or 64k 9 bits), 32k 16 (or 32k 18 bits), 16k 32 (or 16k 36 bits), 8k 64 (or 8k 72 bits), and 4k 128 (or 4k 144 bits). the 4k 128 configuration is unavailable in true dual-port mode because there are a total of 144 data output drivers in the block. mixed-widt h configurations are al so possible, allowing different read and write widths. tables 2?8 and 2?9 summarize the possible m-ram block configurations: table 2?8. m-ram block configur ations (simple dual-port) read port write port 64k 932k 18 16k 36 8k 72 4k 144 64k 9 vvvv 32k 18 vvvv 16k 36 vvvv 8k 72 vvvv 4k 144 v altera corporation 2?35 july 2005 stratix device handbook, volume 1 stratix architecture the read and write operation of the memory is controlled by the wren signal, which sets the ports into either read or write modes. there is no separate read enable ( re ) signal. writing into ram is controlled by both the wren and byte enable ( byteena ) signals for each port. the default value for the byteena signal is high, in which case writing is controlled only by the wren signal. the byte enables are available for th e 18, 36, and 72 modes. in the 144 simple dual-port mode, the two sets of byteena signals ( byteena_a and byteena_b ) are combined to form the necessary 16 byte enables. tables 2?10 and 2?11 summarize the byte selection. table 2?9. m-ram block confi gurations (true dual-port) port a port b 64k 932k 18 16k 36 8k 72 64k 9 vvvv 32k 18 vvvv 16k 36 vvvv 8k 72 vvvv table 2?10. byte enable for m-ram blocks notes (1) , (2) byteena[3..0] datain 18 datain 36 datain 72 [0] = 1 [8..0] [8..0] [8..0] [1] = 1 [17..9] [17..9] [17..9] [2] = 1 ? [26..18] [26..18] [3] = 1 ? [35..27] [35..27] [4] = 1 ? ? [44..36] [5] = 1 ? ? [53..45] [6] = 1 ? ? [62..54] [7] = 1 ? ? [71..63] 2?36 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory similar to all ram blocks, m-ram bloc ks can have different clocks on their inputs and output s. all input registers? renwe , datain , address, and byte enable registers?are clocke d together from either of the two clocks feeding the block. the output register can be bypassed. the eight labclk signals or local interconnect can drive the control signals for the a and b ports of the m-ram block. les can also control the clock_a , clock_b , renwe_a , renwe_b , clr_a , clr _b , clocken_a , and clocken_b signals as shown in figure 2?19 . table 2?11. m-ram combined byte selection for 144 mode notes (1) , (2) byteena[15..0] datain 144 [0] = 1 [8..0] [1] = 1 [17..9] [2] = 1 [26..18] [3] = 1 [35..27] [4] = 1 [44..36] [5] = 1 [53..45] [6] = 1 [62..54] [7] = 1 [71..63] [8] = 1 [80..72] [9] = 1 [89..81] [10] = 1 [98..90] [11] = 1 [107..99] [12] = 1 [116..108] [13] = 1 [125..117] [14] = 1 [134..126] [15] = 1 [143..135] notes to tables 2?10 and 2?11 : (1) any combination of byte enables is possible. (2) byte enables can be used in the sa me manner with 8-bit words, i.e., in 16, 32, 64, and 128 modes. altera corporation 2?37 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?19. m-ram block control signals one of the m-ram block?s horizontal sides drive the address and control signal (clock, renwe, byteena, etc.) inputs. typically, the horizontal side closest to the device perimeter contains the interfaces. the one exception is when two m-ram blocks are paired ne xt to each other. in this case, the side of the m-ram block opposite the common side of the two blocks contains the input interface. the top and bottom sides of any m-ram block contain data input and output in terfaces to the logic array. the top side has 72 data inputs and 72 data ou tputs for port b, and the bottom side has another 72 data inputs and 72 data outputs for port a. figure 2?20 shows an example floorplan for the ep1s60 device and the location of the m-ram interfaces. clocken_a clock_b clock_a clocken_b aclr_a aclr_b dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect renwe_a renwe_b 8 local interconnect local interconnect local interconnect local interconnect 2?38 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory figure 2?20. ep1s60 device with m-ram interface locations note (1) note to figure 2?20 : (1) device shown is an ep1s60 device. the number and position of m-ram blocks varies in other devices. the m-ram block local interconnect is driven by the r4, r8, c4, c8, and direct link interconnects from ad jacent labs. for independent m-ram blocks, up to 10 direct link address and control signal input connections to the m-ram block are possible from the left adjacent labs for m-ram m-ram block m-ram block dsp blocks dsp blocks m4k blocks m512 blocks labs m-ram block m-ram block m-ram block m-ram block m-ram pairs interface to top, bottom, and side opposite of block-to-block border. independent m-ram blocks interface to top, bottom, and side facing device perimeter for easy access to horizontal i/o pins. altera corporation 2?39 july 2005 stratix device handbook, volume 1 stratix architecture blocks facing to the left, and another 10 possible from the right adjacent labs for m-ram blocks facing to the right. for column interfacing, every m-ram column unit connects to the ri ght and left column lines, allowing each m-ram column unit to communicat e directly with three columns of labs. figures 2?21 through 2?23 show the interface between the m-ram block and the logic array. 2?40 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory figure 2?21. left-facing m-ram to interconnect interface notes (1) , (2) notes to figure 2?21 : (1) only r24 and c16 interconnects cross the m-ram block boundaries. (2) the right-facing m-ram block has interf ace blocks on the right side, but none on the left. b1 to b6 and a1 to a6 orientation is clipped across the vertical axis for right-facing m-ram blocks. m-ram block port b port a row unit interface allows lab rows to drive address and control signals to m-ram block column interface block allows lab columns to drive datain and dataout to and from m-ram block labs in row m-ram boundary labs in column m-ram boundary m512 ram block columns column interface block drives to and from c4 and c8 interconnects lab interface blocks r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b6 altera corporation 2?41 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?22. m-ram row unit interface to interconnect lab row interface block m-ram block 10 up to 24 addressa addressb renwe_a renwe_b byteena a [ ] byteena b [ ] clocken_a clocken_b clock_a clock_b aclr_a aclr_b m-ram block to lab row interface block interconnect region r4 and r8 interconnects c4 and c8 interconnects direct link interconnects 2?42 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory figure 2?23. m-ram column unit interface to interconnect 12 12 column interface block m-ram block to lab row interface block interconnec t region datain dataout lab lab lab c4 and c8 interconnects m-ram block altera corporation 2?43 july 2005 stratix device handbook, volume 1 stratix architecture table 2?12 shows the input and output data signal connections for the column units (b1 to b6 and a1 to a6). it also shows the address and control signal input connections to the row units (r1 to r11). table 2?12. m-ram row & column interface unit signals unit interface block input signals output signals r1 addressa[7..0] r2 addressa[15..8] r3 byte_enable_a[7..0] renwe_a r4 - r5 - r6 clock_a clocken_a clock_b clocken_b r7 - r8 - r9 byte_enable_b[7..0] renwe_b r10 addressb[15..8] r11 addressb[7..0] b1 datain_b[71..60] dataout_b[71..60] b2 datain_b[59..48] dataout_b[59..48] b3 datain_b[47..36] dataout_b[47..36] b4 datain_b[35..24] dataout_b[35..24] b5 datain_b[23..12] dataout_b[23..12] b6 datain_b[11..0] dataout_b[11..0] a1 datain_a[71..60] dataout_a[71..60] a2 datain_a[59..48] dataout_a[59..48] a3 datain_a[47..36] dataout_a[47..36] a4 datain_a[35..24] dataout_a[35..24] a5 datain_a[23..12] dataout_a[23..12] a6 datain_a[11..0] dataout_a[11..0] 2?44 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory independent clock mode the memory blocks implement indepe ndent clock mode for true dual- port memory. in this mode, a separate clock is available for each port (ports a and b). clock a controls all registers on the port a side, while clock b controls all registers on the port b side. each port, a and b, also supports independent clock enables and asynchronous clear signals for port a and b registers. figure 2?24 shows a trimatrix memory block in independent clock mode. altera corporation 2?45 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?24. independent clock mode notes (1) , (2) notes to figure 2?24 (1) all registers shown have asynchronous clear ports. (2) violating the setup or hold time on the address registers could corrupt the memory contents. this applies to both read and write operations. 8 d ena q d ena q d ena q data a [ ] address a [ ] memory block 256 16 (2) 512 8 1,024 4 2,048 2 4,096 1 data in address a write/read enable data out data in address b write/read enable data out clken a clock a d ena q wren a 8 lab row clocks q a [ ] 8 data b [ ] address b [ ] clken b clock b wren b q b [ ] ena ab ena d q d ena q byteena a [ ] byte enable a byte enable b byteena b [ ] ena d q ena d q ena d q d q write pulse generator write pulse generator 2?46 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory input/output clock mode input/output clock mode can be im plemented for both the true and simple dual-port memory modes. on ea ch of the two ports, a or b, one clock controls all registers for inputs into the memory block: data input, wren , and address. the other clock co ntrols the block?s data output registers. each memory block port, a or b, also supports independent clock enables and asynchronous cl ear signals for input and output registers. figures 2?25 and 2?26 show the memory block in input/output clock mode. altera corporation 2?47 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?25. input/output clock m ode in true dual-port mode notes (1) , (2) notes to figure 2?25 : (1) all registers shown have asynchronous clear ports. (2) violating the setup or hold time on the address registers could corrupt the memory contents. this applies to both read and write operations. 8 d ena q d ena q d ena q data a [ ] address a [ ] memory block 256 16 ( 2 ) 512 8 1,024 4 2,04 8 2 4,096 1 data in address a write/read enable data out data in address b write/read enable data out clken a clock a d ena q wren a 8 lab row clocks q a [ ] 8 data b [ ] address b [ ] clken b clock b wren b q b [ ] ena ab ena d q ena d q ena d q d q d ena q byteena a [ ] byte enable a byte enable b byteena b [ ] ena d q write pulse generator write pulse generator 2?48 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory figure 2?26. input/output clock mode in simple dual-port mode notes (1) , (2) notes to figure 2?26 : (1) all registers shown except the rden register have asynchronous clear ports. (2) violating the setup or hold time on the address register s could corrupt the memory contents. this applies to both read and write operations. 8 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q wraddress[ ] address[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in read address write address write enable read enable data out outclken inclken wrclock rdclock wren rden 8 lab row clocks to multitrac k interconnect d ena q byteena[ ] byte enable write pulse generator altera corporation 2?49 july 2005 stratix device handbook, volume 1 stratix architecture read/write clock mode the memory blocks implement read/w rite clock mode for simple dual- port memory. you can use up to two cl ocks in this mode. the write clock controls the block?s data inputs, wraddress , and wren . the read clock controls the data output, rdaddress , and rden . the memory blocks support independent clock enables for each clock and asynchronous clear signals for the read- and write-side registers. figure 2?27 shows a memory block in read/write clock mode. 2?50 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory figure 2?27. read/write clock m ode in simple dual-port mode notes (1) , (2) notes to figure 2?27 : (1) all registers shown except the rden register have asynchronous clear ports. (2) violating the setup or hold time on the address register s could corrupt the memory contents. this applies to both read and write operations. 8 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q wraddress[ ] address[ ] memory block 256 16 512 8 1,024 4 2,04 8 2 4,096 1 data in read address write address write enable read enable data out outclken inclken wrclock rdclock wren rden 8 lab row clocks to multitrac k interconnect d ena q byteena[ ] byte enable write pulse generator altera corporation 2?51 july 2005 stratix device handbook, volume 1 stratix architecture single-port mode the memory blocks also support single-port mode, used when simultaneous reads and writes are not required. see figure 2?28 . a single block in a memory block can support up to two single-port mode ram blocks in the m4k ram bloc ks if each ram block is less than or equal to 2k bits in size. figure 2?28. single-port mode note (1) note to figure 2?28 : (1) violating the setup or hold time on the address register s could corrupt the memory contents. this applies to both read and write operations. 8 d ena q d ena q d ena q d ena q data[ ] address[ ] ram/rom 256 16 512 8 1,024 4 2,04 8 2 4,096 1 data in address write enable data out outclken inclken inclock outclock write pulse generator wren 8 lab row clocks to multitrac k interconnect 2?52 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block digital signal processing block the most commonly used dsp function s are finite impuls e response (fir) filters, complex fir filter s, infinite impulse response (iir) filters, fast fourier transform (fft) functions, direct cosine transform (dct) functions, and correlators. all of th ese blocks have the same fundamental building block: the multiplier. additionally, some applications need specialized operations such as mul tiply-add and multiply-accumulate operations. stratix devices provide dsp blocks to meet the arithmetic requirements of these functions. each stratix device has two column s of dsp blocks to efficiently implement dsp functions faster than le-based implementations. larger stratix devices have more dsp blocks per column (see table 2?13 ). each dsp block can be configur ed to support up to: eight 9 9-bit multipliers four 18 18-bit multipliers one 36 36-bit multiplier as indicated, the stratix dsp block can support one 36 36-bit multiplier in a single dsp block. this is true for any matched sign multiplications (either unsigned by unsigned or signed by signed), but the capabilities for dynamic and mixed sign multiplications are handled differently. the following list provides the largest func tions that can fit into a single dsp block. 36 36-bit unsigned by unsigned multiplication 36 36-bit signed by signed multiplication 35 36-bit unsigned by signed multiplication 36 35-bit signed by unsigned multiplication 36 35-bit signed by dynamic sign multiplication 35 36-bit dynamic sign by signed multiplication 35 36-bit unsigned by dy namic sign multiplication 36 35-bit dynamic sign by unsigned multiplication 35 35-bit dynamic sign multiplicati on when the sign controls for each operand are different 36 36-bit dynamic sign multiplication when the same sign control is used for both operands 1 this list only shows functions that can fit into a single dsp block. multiple dsp blocks can support larger multiplication functions. figure 2?29 shows one of the columns with surrounding lab rows. altera corporation 2?53 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?29. dsp blocks arranged in columns dsp block column 8 lab rows dsp block 2?54 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block table 2?13 shows the number of dsp blocks in each stratix device. dsp block multipliers can optionally feed an adder/subtractor or accumulator within the block depend ing on the configuration. this makes routing to les easier, saves le routing resources, and increases performance, because al l connections and blocks are within the dsp block. additionally, the dsp bloc k input registers can efficiently implement shift registers for fir filter applications. figure 2?30 shows the top-level diagram of the dsp block configured for 18 18-bit multiplier mode. figure 2?31 shows the 9 9-bit multiplier configuration of the dsp block. table 2?13. dsp blocks in stratix devices notes (1) , (2) device dsp blocks total 9 9 multipliers total 18 18 multipliers total 36 36 multipliers ep1s10 6 48 24 6 ep1s20 10 80 40 10 ep1s25 10 80 40 10 ep1s30 12 96 48 12 ep1s40 14 112 56 14 ep1s60 18 144 72 18 ep1s80 22 176 88 22 notes to ta b l e 2 ? 1 3 : (1) each device has either the number of 9 9-, 18 18-, or 36 36-bit multipliers shown. the total number of multipliers for each device is not the sum of all the multipliers. (2) the number of supported multiply fu nctions shown is base d on signed/signed or unsigned/unsigned implementations. altera corporation 2?55 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?30. dsp block diagram for 18 18-bit configuration adder/ subtractor/ accumulator 2 adder/ subtractor/ accumulator 1 summation opt ion a l p i pe lin e reg i ster stage m ul t i p li er stage o u tp u t se l ect ion m ul t i p l e x er opt ion a l o u tp u t reg i ster stage clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena opt ion a l ser i a l s hi ft reg i ster in p u ts fr o m pre viou s dsp b lo c k opt ion a l stage c on f i g u rab l e as a cc u m ul at o r o r d yn am i c a dder / s u btract o r s u mmat ion stage f o r a dd in g fou r m ul t i p li ers to get h er opt ion a l in p u t reg i ster stage wi t h para ll e l in p u t o r s hi ft reg i ster c on f i g u rat ion opt ion a l ser i a l s hi ft reg i ster o u tp u ts t o n e x t dsp b lo c k in t h e c olu m n to multitrack interconnect 2?56 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block figure 2?31. dsp block diagram for 9 9-bit configuration clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 1a summation summation clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 1b clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 2a clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 2b clrn dq ena clrn dq ena clrn dq ena output selection multiplexer to multitrack interconnect altera corporation 2?57 july 2005 stratix device handbook, volume 1 stratix architecture the dsp block consists of the following elements: multiplier block adder/output block multiplier block the dsp block multiplier block cons ists of the input registers, a multiplier, and pipeline register fo r pipelining multiply-accumulate and multiply-add/subtract functions as shown in figure 2?32 . figure 2?32. multiplier sub-bloc k within stratix dsp block note to figure 2?32 : (1) these signals can be unregister ed or registered once to match data path pipelines if required. clrn dq ena data a data b result to adder blocks shiftout b shiftout a shiftin a shiftin b aclr[3..0] clock[3..0] ena[3..0] optional multiply-accumulate and multiply-add pipeline sign_a (1) sign_b (1) clrn dq ena clrn dq ena 2?58 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block input registers a bank of optional input registers is located at the input of each multiplier and multiplicand inputs to the multi plier. when these registers are configured for parallel data inputs, they are driven by regular routing resources. you can use a clock signal, asynchronous clear signal, and a clock enable signal to independently control each set of a and b inputs for each multiplier in the dsp block. you select these control signals from a set of four different clock[3..0] , aclr[3..0] , and ena[3..0] signals that drive the entire dsp block. you can also configure the input registers for a shift register application. in this case, the input registers feed the multiplier and drive two dedicated shift output lines: shiftouta and shiftoutb . the shift outputs of one multiplier block direct ly feed the adjacent multiplier block in the same dsp block (or the next dsp block) as shown in figure 2?33 , to form a shift register chain. this chai n can terminate in an y block, that is, you can create any length of shift regi ster chain up to 224 registers. you can use the input shift registers for fir filter applications. one set of shift inputs can provide data for a filter, and the other are coefficients that are optionally loaded in serial or para llel. when implementing 9 9- and 18 18-bit multipliers, you do not need to implement external shift registers in lab les. you implement all the filter circuitry within the dsp block and its routing resources, savi ng le and general routing resources for general logic. external registers are needed for shift register inputs when using 36 36-bit multipliers. altera corporation 2?59 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?33. multiplier sub-blocks usin g input shift register connections note (1) note to figure 2?33 : (1) either data a or data b input can be set to a parallel input for constant coefficient multiplication. clrn dq ena data a data b a[n] b[n] clrn dq ena clrn dq ena clrn dq ena data a data b a[n e 1] b[n e 1] clrn dq ena clrn dq ena clrn dq ena data a data b a[n e 2] b[n e 2] clrn dq ena clrn dq ena 2?60 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block table 2?14 shows the summary of input register modes for the dsp block. multiplier the multiplier supports 9 9-, 18 18-, or 36 36-bit multiplication. each dsp block supports eight possible 9 9-bit or smaller multipliers. there are four multiplier blocks available for multipliers larger than 9 9 bits but smaller than 18 18 bits. there is one multiplier block available for multipliers larger than 18 18 bits but smaller than or equal to 36 36 bits. the ability to have several small multipliers is useful in applications such as video processing. large mult ipliers greater than 18 18 bits are useful for applications such as the mantissa multiplication of a single- precision floating-point number. the multiplier operands can be sign ed or unsigned numbers, where the result is signed if either input is signed as shown in table 2?15 . the sign_a and sign_b signals provide dynamic control of each operand?s representation: a logic 1 indicates the operand is a signed number, a logic 0 indicates the operand is an unsigned number. these sign signals affect all multipliers and adders within a si ngle dsp block and you can register them to match the data path pipeline. the multipliers are full precision (that is, 18 bits for the 18-bit multiply , 36-bits for the 36-bit multiply, and so on) regardless of whether sign_a or sign_b set the operands as signed or unsigned numbers. table 2?14. input register modes register input mode 9 9 18 18 36 36 parallel input vvv shift register input vv table 2?15. multiplier signed representation data a data b result unsigned unsigned unsigned unsigned signed signed signed unsigned signed signed signed signed altera corporation 2?61 july 2005 stratix device handbook, volume 1 stratix architecture pipeline/post multiply register the output of 9 9- or 18 18-bit mult ipliers can optionally feed a register to pipeline multiply-accu mulate and multiply-add/ subtract functions. for 36 36-bit multipliers, this register will pipeline the multiplier function. adder/output blocks the result of the multiplier sub-blocks are sent to the adder/output block which consist of an adder/subtrac tor/accumulator unit , summation unit, output select multiplexer, and output registers. the results are used to configure the adder/output block as a pure output, accu mulator, a simple two-multiplier adder, four-multiplier adder, or final stage of the 36-bit multiplier. you can configure the adder/output bloc k to use output registers in any mode, and must use output registers for the accumulator. the system cannot use adder/output blocks independently of the multiplier. figure 2?34 shows the adder and output stages. 2?62 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block figure 2?34. adder/o utput blocks note (1) notes to figure 2?34 : (1) adder/output block shown in figure 2?34 is in 18 18-bit mode. in 9 9-bit mode, there are four adder/subtractor blocks and two summation blocks. (2) these signals are either not registered, registered once , or registered twice to match the data path pipeline. adder/ subtractor/ accumulator1 summation result a result b result c result d addnsub1 ( 2 ) accum_sload0 ( 2 ) addnsub3 ( 2 ) si g na ( 2 ) si g nb ( 2 ) accum_sload1 ( 2 ) a cc u m ul at o r f eedbac k a cc u m ul at o r f eedbac k overflow0 adder/ subtractor/ accumulator2 o u tp u t se l ect io n m ul t i p l e x er o u tp u t reg i ster b lo c k overflow1 altera corporation 2?63 july 2005 stratix device handbook, volume 1 stratix architecture adder/subtractor/accumulator the adder/subtractor/accumulator is the first level of the adder/output block and can be used as an accumul ator or as an adder/subtractor. adder/subtractor each adder/subtractor/accumulator block can perform addition or subtraction using the addnsub independent control signal for each first- level adder in 18 18-bit mode. there are two addnsub[1..0] signals available in a dsp block for any configuration. for 9 9-bit mode, one addnsub[1..0] signal controls the top two one-level adders and another addnsub[1..0] signal controls the bottom two one-level adders. a high addnsub signal indicates addition, and a low signal indicates subtraction. the addnsub control signal can be unregistered or registered once or twice when feed ing the adder blocks to match data path pipelines. the signa and signb signals serve the same function as the multiplier block signa and signb signals. the only difference is that these signals can be registered up to two times. these signals are tied to the same signa and signb signals from the multiplier and must be connected to the same clocks and control signals. accumulator when configured for accumulation, th e adder/output block output feeds back to the accumulator as shown in figure 2?34 . the accum_sload[1..0] signal synchronously loads the multiplier result to the accumulator output. this signal can be unregistered or registered once or twice. additionally, the overflow signal indicates the accumulator has overflowed or underflowed in accumulation mode. this signal is always registered and must be externally latched in les if the design requires a latched overflow signal. summation the output of the adder/subtract or/accumulator block feeds to an optional summation block. this bloc k sums the outputs of the dsp block multipliers. in 9 9-bit mode, there are two su mmation blocks providing the sums of two sets of four 9 9-bi t multipliers. in 18 18-bit mode, there is one summation providing the sum of one set of four 18 18-bit multipliers. 2?64 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block output selection multiplexer the outputs from the various elemen ts of the adder/output block are routed through an output selection multiplexer. based on the dsp block operational mode and user settings, the multiplexer selects whether the output from the multiplier, the adder/subtractor/accumulator, or summation block feeds to the output. output registers optional output registers for the dsp block outputs are controlled by four sets of control signals: clock[3..0] , aclr[3..0] , and ena[3..0] . output registers can be used in any mode. modes of operation the adder, subtractor, and accumulate functions of a dsp block have four modes of operation: simple multiplier multiply-accumulator two-multipliers adder four-multipliers adder 1 each dsp block can only support one mode. mixed modes in the same dsp block is not supported. simple multiplier mode in simple multiplier mode, the dsp block drives the multiplier sub-block result directly to the output with or without an output register. up to four 18 18-bit multipliers or eight 9 9-bit multipliers can drive their results directly out of one dsp block. see figure 2?35 . altera corporation 2?65 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?35. simple multiplier mode note to figure 2?35 : (1) these signals are not registered or regist ered once to match the data path pipeline. dsp blocks can also implement one 36 36-bit multiplier in multiplier mode. dsp blocks use four 18 18-bit multipliers combined with dedicated adder and internal shift circuitry to achieve 36-bit multiplication. the input shift regist er feature is not available for the 36 36-bit multiplier. in 36 36-bit mo de, the device can use the register that is normally a multiplier-result-out put register as a pipeline stage for the 36 36-bit multiplier. figure 2?36 shows the 36 36-bit multiply mode. clrn dq ena data a data b data out shiftout b shiftout a shiftin a shiftin b aclr clock ena signa (1) signb (1) clrn dq ena clrn dq ena clrn dq ena 2?66 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block figure 2?36. 36 36 multiply mode notes to figure 2?36 : (1) these signals are not registered or registered once to match the pipeline. (2) these signals are not registered, registered once, or registered twice for latency to match the pipeline. clrn dq ena a[17..0] a[17..0] b[17..0] b[17..0] a[35..18] a[35..18] b[35..18] b[35..18] aclr clock ena si g na (1) si g nb (1) clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena data ou t 36 36 multiplier adder si g na ( 2 ) si g nb ( 2 ) altera corporation 2?67 july 2005 stratix device handbook, volume 1 stratix architecture multiply-accumulator mode in multiply-accumulator mode (see figure 2?37 ), the dsp block drives multiplied results to the adder/subtra ctor/accumulator block configured as an accumulator. you can implement one or two multiply-accumulators up to 18 18 bits in one dsp block. the first and third multiplier sub- blocks are unused in this mode, beca use only one multiplier can feed one of two accumulators. the multiply-ac cumulator output can be up to 52 bits?a maximum of a 36-bit result with 16 bits of accumulation. the accum_sload and overflow signals are only available in this mode. the addnsub signal can set the accumulator for decimation and the overflow signal indicates underflow condition. figure 2?37. multiply -accumulate mode notes to figure 2?37 : (1) these signals are not registered or regist ered once to match the data path pipeline. (2) these signals are not registered, regi stered once, or registered twice for la tency to match the data path pipeline. two-multipliers adder mode the two-multipliers adder mode uses the adder/subtractor/accumulator block to add or subtract the outputs of the multiplier block, which is useful for applications such as fft functions and complex fir filters. a clrn dq ena clrn dq ena data a data b data out overflow shiftout b shiftout a shiftin a shiftin b aclr clock ena signa (1) signb (1) clrn dq ena clrn dq ena accumulator addnsub (2) signa (2) signb (2) accum_sload (2) 2?68 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block single dsp block can implement tw o sums or differences from two 18 18-bit multipliers each or four s ums or differences from two 9 9-bit multipliers each. you can use the two-multipliers adder mode for complex multiplications, which are written as: (a + jb) (c + jd) = [(a c) ? (b d)] + j [(a d) + (b c)] the two-multipliers adder mode allows a single dsp block to calculate the real part [(a c) ? (b d)] using one subtractor and the imaginary part [(a d) + (b c)] using one adder, fo r data widths up to 18 bits. two complex multiplications are possible for data widths up to 9 bits using four adder/subtractor/accumulator blocks. figure 2?38 shows an 18-bit two-multipliers adder. figure 2?38. two-multipliers adder m ode implementing complex multiply four-multipliers adder mode in the four-multipliers adder mode, th e dsp block adds the results of two first -stage adder/subtractor bl ocks. one sum of four 18 18-bit multipliers or two different sums of tw o sets of four 9 9-bit multipliers can be implemented in a single dsp block. the product width for each multiplier must be the same size. th e four-multipliers adder mode is useful for fir filter applications. figure 2?39 shows the four multipliers adder mode. subtractor 36 36 18 18 18 37 a 18 (a c) ? (b d) (real part) adder 36 36 18 18 37 a 18 18 18 (a d) + (b c) (imaginary part) 18 18 18 dsp block c b d d b c altera corporation 2?69 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?39. four-multipliers adder mode notes to figure 2?39 : (1) these signals are not registered or regist ered once to match the data path pipeline. (2) these signals are not registered, regi stered once, or registered twice for la tency to match the data path pipeline. clrn dq ena data a data b shiftin a shiftin b aclr clock ena si g na (1) si g nb (1) clrn dq ena clrn dq ena clrn dq ena data a data b clrn dq ena clrn dq ena adder/subtractor clrn dq ena data a data b clrn dq ena clrn dq ena clrn dq ena data a data b shiftout b shiftout a clrn dq ena clrn dq ena adder/subtractor addnsub1 ( 2 ) si g na ( 2 ) si g nb ( 2 ) clrn dq ena data ou t addnsub3 ( 2 ) summation 2?70 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block for fir filters, the dsp block combines the four-multipliers adder mode with the shift register inputs. one set of shift inputs contains the filter data, while the other holds the coefficients loaded in serial or parallel. the input shift register eliminates the need for shift registers external to the dsp block (i.e., implemented in les). th is architecture simplifies filter design since the dsp block implemen ts all of the filter circuitry. one dsp block can implement an entire 18-bit fir filter with up to four taps. for fir filters larger than four taps, dsp blocks can be cascaded with additional adder stages implemented in les. table 2?16 shows the different number of multipliers possible in each dsp block mode according to size. these modes allow the dsp blocks to implement numerous applications for dsp including ffts, complex fir, fir, and 2d fir filters, equalizers, iir, correlators, matrix multiplication and many other functions. dsp block interface stratix device dsp block outputs can cascade down within the same dsp block column. dedicated connections between dsp blocks provide fast connections between the shift register inputs to cascade the shift register chains. you can cascade dsp blocks for 9 9- or 18 18-bit fir filters larger than four taps, with additional adder stages implemented in les. if the dsp block is configured as 36 36 bits, the adder, subtractor, or accumulator stages are implemented in les. each dsp block can route the shift register chain out of the bl ock to cascade two full columns of dsp blocks. table 2?16. multiplier size & c onfigurations per dsp block dsp block mode 9 9 18 18 36 36 (1) multiplier eight multipliers with eight product outputs four multipliers with four product outputs one multiplier with one product output multiply-accumulator two multiply and accumulate (52 bits) two multiply and accumulate (52 bits) ? two-multipliers adder four sums of two multiplier products each two sums of two multiplier products each ? four-multipliers adder two sums of four multiplier products each one sum of four multiplier products each ? note to table 2?16 : (1) the number of supported multiply functions shown is based on signed/sig ned or unsigned/unsigned implementations. altera corporation 2?71 july 2005 stratix device handbook, volume 1 stratix architecture the dsp block is divided into eight bl ock units that interface with eight lab rows on the left and right. each block unit can be considered half of an 18 18-bit multiplier sub-block with 18 inputs and 18 outputs. a local interconnect region is associated with each dsp block. like an lab, this interconnect region can be fed with 10 direct link interconnects from the lab to the left or right of the dsp block in the same row. all row and column routing resources can access the dsp block?s local interconnect region. the outputs also work sim ilarly to lab outputs as well. nine outputs from the dsp block can drive to the left lab through direct link interconnects and nine can drive to the right lab though direct link interconnects. all 18 outputs can drive to all types of row and column routing. outputs can drive right- or left-column routing. figures 2?40 and 2?41 show the dsp block interfaces to lab rows. figure 2?40. dsp block interconnect interface a1[17..0] b1[17..0] a2[17..0] b2[17..0] a3[17..0] b3[17..0] a4[17..0] b4[17..0] oa[17..0] ob[17..0] oc[17..0] od[17..0] oe[17..0] of[17..0] og[17..0] oh[17..0] dsp b lo c k m ul t it rac k in terc onn ec t m ul t it rac k in terc onn ect 2?72 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block figure 2?41. dsp block interface to interconnect a bus of 18 control signals feeds the entire dsp block. these signals include clock[0..3] clocks, aclr[0..3] asynchronous clears, ena[1..4] clock enables, signa , signb signed/unsigned control signals, addnsub1 and addnsub3 addition and subtraction control signals, and accum_sload[0..1] accumulator synchronous loads. the lab lab row interface block dsp block row structure 10 [17..0] [17..0] dsp b lo c k t o la b r ow in terface b lo c k in terc onn ect reg ion 1 8 in p u ts per r ow 1 8 o u tp u ts per r ow r 4 a n d r8 in terc onn ects c 4 a n d c8 in terc onn ects d i rect link in terc onn ect fr o m a djace n t la b nin e d i rect link o u tp u ts t o a djace n t la bs d i rect link in terc onn ect fr o m a djace n t la b 18 18 18 control 3 9 9 10 altera corporation 2?73 july 2005 stratix device handbook, volume 1 stratix architecture clock signals are routed from lab row clocks and are generated from specific lab rows at the dsp block interface. the lab row source for control signals, data inputs, and outputs is shown in table 2?17 . plls & clock networks stratix devices provide a hierarchical clock structure and multiple plls with advanced features. the large number of clocking resources in combination with the clock synthesi s precision provid ed by enhanced and fast plls provides a comple te clock management solution. global & hierarchical clocking stratix devices provide 16 dedicated global clock networks, 16 regional clock networks (four per device quadrant), and 8 dedicated fast regional clock networks (for ep1s10, ep 1s20, and ep1s25 devices), and 16 dedicated fast regional clock networks (for ep1s30 ep1s40, and ep1s60, and ep1s80 devices). th ese clocks are organized into a hierarchical clock structure that allo ws for up to 22 clocks per device region with low skew and delay. this hierarchical clocking scheme provides up to 48 unique clock domains within stratix devices. table 2?17. dsp block signal sources & destinations lab row at interface control signals generated data inputs data outputs 1 signa a1[17..0] oa[17..0] 2 aclr0 accum_sload0 b1[17..0] ob[17..0] 3 addnsub1 clock0 ena0 a2[17..0] oc[17..0] 4 aclr1 clock1 ena1 b2[17..0] od[17..0] 5 aclr2 clock2 ena2 a3[17..0] oe[17..0] 6 sign_b clock3 ena3 b3[17..0] of[17..0] 7 clear3 accum_sload1 a4[17..0] og[17..0] 8 addnsub3 b4[17..0] oh[17..0] 2?74 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks there are 16 dedicated clock pins ( clk[15..0] ) to drive either the global or regional clock networks . four clock pins drive each side of the device, as shown in figure 2?42 . enhanced and fast pll outputs can also drive the global and region al clock networks. global clock network these clocks drive throughout the entire device, feeding all device quadrants. the global clock networks can be used as clock sources for all resources within the device?ioes, les, dsp blocks, and all memory blocks. these resources can also be used for control signals, such as clock enables and synchronous or asynchrono us clears fed from the external pin. the global clock networks can al so be driven by internal logic for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. figure 2?42 shows the 16 dedicated clk pins driving global clock networks. altera corporation 2?75 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?42. global clocking note (1) note to figure 2?42 : (1) the corner fast plls can also be driv en through the global or regional clock networks. the global or regional clock in put to the fast pll can be driven by an output from another pll, a pin-driven gl obal or regional clock, or internally- generated global signals. regional clock network there are four regional clock networks within each quadrant of the stratix device that are driven by the same dedicated clk[15..0] input pins or from pll outputs. from a top view of the silicon, rclk[0..3] are in the top left quadrant, rclk[8..11] are in the top-right quadrant, rclk[4..7] are in the bottom-left quadrant, and rclk[12..15] are in the bottom-right quadrant. the region al clock networks only pertain to the quadrant they drive into. the re gional clock networks provide the lowest clock delay and skew for logic contained within a single quadrant. rclk cannot be driven by internal logic. the clk clock pins symmetrically drive the rclk networks within a particular quadrant, as shown in figure 2?43 . see figures 2?50 and 2?51 for rclk connections from plls and clk pins. global clock [15..0] clk[15..12] clk[3..0] clk[7..4] clk[11..8] global clock [15..0] 2?76 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks figure 2?43. regional clocks fast regional clock network in ep1s25, ep1s20, and ep 1s10 devices, there are two fast regional clock networks, fclk[1..0] , within each quadrant, fed by input pins that can connect to fast regional clock networks (see figure 2?44 ). in ep1s30 and larger devices, there are two fast re gional clock networks within each half-quadrant (see figure 2?45 ). dual-purpose fclk pins drive the fast clock networks. all devices have eight fclk pins to drive fast regional clock networks. any i/o pin can drive a clock or control signal onto any fast regional clock network with the ad dition of a delay. this signal is driven via the i/o interconnect. the fa st regional clock networks can also be driven from internal logic elements. rc lk[1..0] rc lk[4.. 5 ] rc lk[ 6 ..7] rc lk[1 2 ..13] rc lk[ 2 ..3] rc lk[11..10] rc lk[14..1 5 ] rc lk[9.. 8 ] clk[15..12] clk[3..0] clk[7..4] clk[11..8] reg ion a l c lo c k s o nly dr iv e a de vi ce qu adra n t fr o m spec i f i ed c lk p in s o r p ll s wi t hin t h at qu adra n t altera corporation 2?77 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?44. ep1s25, ep1s20 & ep1s10 devi ce fast clock pi n connections to fast regional clocks notes to figure 2?44 : (1) this is a set of two multiplexers. (2) in addition to the fclk pin inputs, there is also an input from the i/o interconnect. fclk[1..0] fclk[1..0] fclk[1..0] fclk[1..0] fclk[1..0] fclk[7..6] fclk[5..4] fclk[3..2] 22 22 22 22 (1), (2) (1), (2) (1), (2) (1), (2) 2?78 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks figure 2?45. ep1s30 device fast regiona l clock pin connections to fast regional clocks notes to figure 2?45 : (1) this is a set of two multiplexers. (2) in addition to the fclk pin inputs, there is also an input from the i/o interconnect. combined resources within each region, there are 22 dist inct dedicated clocking resources consisting of 16 global clock lines, fo ur regional clock lines, and two fast regional clock lines. multiplexers are used with these clocks to form eight bit busses to drive lab row clocks, co lumn ioe clocks, or row ioe clocks. another multiplexer is used at the lab level to select two of the eight row clocks to feed the le regi sters within the lab. see figure 2?46 . fclk[1..0] fclk4 fclk5 fclk2 fclk3 fclk6 fclk7 fclk0 fclk1 (1), (2) (1), (2) (1), (2) (1), (2) (1), (2) (1), (2) (1), (2) (1), (2) altera corporation 2?79 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?46. regional clock bus ioe clocks have horizontal and vertical block regi ons that are clocked by eight i/o clock signals chosen from the 22 quadrant or half-quadrant clock resources. figures 2?47 and 2?48 show the quadrant and half- quadrant relationship to the i/o cloc k regions, respectively. the vertical regions (column pins) have less cloc k delay than the horizontal regions (row pins). clock [21..0] vertical i/o cell io_clk[7..0] lab row clock [7..0] horizontal i/o cell io_clk[7..0] global clock network [15..0] fast re g ional clock network [1..0] re g ional clock network [3..0] c lo c k s av a il ab l e t o a qu adra n t o r h a l f -qu adra n t 2?80 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks figure 2?47. ep1s10, ep1s20 & ep1s 25 device i/o clock groups io_clkc[7..0] io_clkf[7..0] io_clke[7..0] io_clka[7..0] io_clkb[7..0] io_clkd[7..0] io_clkh[7..0] io_clkg[7..0] 8 8 22 clocks in the quadrant 22 clocks in the quadrant 22 clocks in the quadrant 22 clocks in the quadrant 8 8 8 8 8 8 i/o clock region s altera corporation 2?81 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?48. ep1s30, ep1s40, ep1s60, ep1s80 device i/o clock groups you can use the quartus ii software to control whether a clock input pin is either global, regional, or fast regional. the quartus ii software automatically selects the clocking resources if not specified. enhanced & fast plls stratix devices provide robust clock management and synthesis using up to four enhanced plls and eight fast plls. these plls increase performance and provid e advanced clock interfacing and clock- frequency synthesis. with features such as clock switchover, spread spectrum clocking, programmable band width, phase and delay control, and pll reconfiguration, the stratix device?s enhanced plls provide you with complete control of your clocks and system timing. the fast plls io_clkj[7: 0 ] io_clki[7: 0 ] io_clka[7: 0 ] io_clkb[7: 0 ] 8 22 clocks in the half-quadrant 22 clocks in the half-quadrant 22 clocks in the half-quadrant 22 clocks in the half-quadrant 22 clocks in the half-quadrant 22 clocks in the half-quadrant 22 clocks in the half-quadrant 22 clocks in the half-quadrant 8 8 8 i/o clock region s io_clkl[7: 0 ] io_clkk[7: 0 ] io_clkc[7: 0 ] io_clkd[7: 0 ] 888 8 8 8 8 8 8 8 8 8 io_clke[7: 0 ] io_clkf[7: 0 ] io_clkg[7: 0 ] io_clkh[7: 0 ] io_clkn[7: 0 ] io_clkm[7: 0 ] io_clkp[7: 0 ] io_clko[7: 0 ] 2?82 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks provide general purpose clocking with multiplication and phase shifting as well as high-speed outputs for hi gh-speed differential i/o support. enhanced and fast plls work togeth er with the stratix high-speed i/o and advanced clock architecture to pr ovide significant improvements in system performance and bandwidth. the quartus ii software enables the plls and their fe atures without requiring any external devices. table 2?18 shows the plls available for each stratix device. table 2?18. stratix device pll availability device fast plls enhanced plls 1234 7 8 9105 (1) 6 (1) 11 (2) 12 (2) ep1s10 vvvv vv ep1s20 vvvv vv ep1s25 vvvv vv ep1s30 vvvv v (3) v (3) v (3) v (3) vv ep1s40 vvvv v (3) v (3) v (3) v (3) vvv (3) v (3) ep1s60 vvvvv v v v vvvv ep1s80 vvvvv v v v vvvv notes to table 2?18 : (1) plls 5 and 6 each have eight single-e nded outputs or four differential outputs. (2) plls 11 and 12 each have one single-ended output. (3) ep1s30 and ep1s40 devices do not support these plls in the 780-pin fineline bga ? package. altera corporation 2?83 july 2005 stratix device handbook, volume 1 stratix architecture table 2?19 shows the enhanced pll and fast pll features in stratix devices. table 2?19. stratix pll features feature enhanced pll fast pll clock multiplication and division m /( n post-scale counter) (1) m /(post-scale counter) (2) phase shift down to 156.25-ps increments (3) , (4) down to 125-ps increments (3) , (4) delay shift 250-ps increments for 3 ns clock switchover v pll reconfiguration v programmable bandwidth v spread spectrum clocking v programmable duty cycle vv number of internal clock outputs 6 3 (5) number of external clock outputs f our differential/eight singled-ended or one single-ended (6) (7) number of feedback clock inputs 2 (8) notes to table 2?19 : (1) for enhanced plls, m, n , range from 1 to 512 and post-scale counters g, l, e range from 1 to 1024 with 50% duty cycle. with a non-50% duty cycle the post-scale counters g, l, e range from 1 to 512. (2) for fast plls, m and post-scale counters range from 1 to 32. (3) the smallest phase shif t is determined by the voltage controlle d oscillator (vco) period divided by 8. (4) for degree increments, stratix devices can shift a ll output frequencies in in crements of at least 45 . smaller degree increments are possible depending on the frequency and divide parameters. (5) plls 7, 8, 9, and 10 have two output ports per pll. plls 1, 2, 3, and 4 have three output ports per pll. (6) every stratix device has two enhanced plls (plls 5 and 6) with either eight sing le-ended outputs or four differential outputs each. two additional enhanced plls (plls 11 and 12) in ep1s80, ep1s60, and ep1s40 devices each have one single-ended output. devices in the 780 p in fineline bga packages do not support plls 11 and 12. (7) fast plls can drive to any i/o pin as an external clock. for high-speed differential i/o pins, the device uses a data channel to generate txclkout . (8) every stratix device has two enhanced plls with one sing le-ended or differential ex ternal feedback input per pll. 2?84 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks figure 2?49 shows a top-level diagram of the stratix device and pll floorplan. figure 2?49. pll locations fpll7clk fpll10cl k fpll9clk clk[8..11] fpll8clk clk[3..0] 7 1 2 8 10 4 3 9 11 5 12 6 clk [ 7..4 ] clk[15..12] p ll s altera corporation 2?85 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?50 shows the global and regional clocking from the pll outputs and the clk pins. figure 2?50. global & regional clock connections fr om side pins & fast pll outputs note (1) , (2) notes to figure 2?50 : (1) plls 1 to 4 and 7 to 10 are fast plls. plls 5, 6, 11, and 12 are enhanced plls. (2) the global or regional clocks in a fast pll?s quadrant can drive the fast pll input. a pin or other pll must drive the global or regional source. the source cannot be driven by internally generated logic before driving the fast pll. figure 2?51 shows the global and regional clocking from enhanced pll outputs and top clk pins. 2 clk0 clk1 clk2 clk3 g0 fpll7clk g1 g2 g3 rclk0 rclk1 rclk4 rclk5 g10 g11 g8 g9 rclk9 rclk8 rclk15 rclk14 g lo ba l c lo c k s reg ion a l c lo c k s pll 7 l 0 l 1 g 0 pll 1 pll 2 fpll8clk pll 8 2 clk10 clk11 clk8 clk9 fpll10cl k pll 10 pll 4 pll 3 fpll9clk pll 9 reg ion a l c lo c k s l 0 l 1 g 0 l 0 l 1 g 0 l 0 l 1 g 0 l 0 l 1 g 0 l 0 l 1 g 0 l 0 l 1 g 0 l 0 l 1 g 0 2?86 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks figure 2?51. global & regional cl ock connections from top cloc k pins & enhanced pll outputs note (1) notes to figure 2?51 : (1) plls 1 to 4 and 7 to 10 are fast plls. plls 5, 6, 11, and 12 are enhanced plls. (2) clk4 , clk6 , clk12 , and clk14 feed the corresponding pll?s inclk0 port. (3) clk5 , clk7 , clk13 , and clk15 feed the corresponding pll?s inclk1 port. (4) the ep1s40 device in the 780-pin fineline bga package does not support plls 11 and 12. g12 g13 g14 g15 rclk10 rclk11 rclk2 rclk3 g7 g6 g5 g4 rclk13 rclk12 rclk7 rclk6 pll 12 l0 l1 g0 g1 g2 g3 clk7 clk6 clk5 clk4 pll 6 g0 g1 g2 g3 l0 l1 pll 11 l0 l1 g0 g1 g2 g3 clk13 clk12 clk14 clk15 pll 5 g0 g1 g2 g3 l0 l1 e[0..3] pll12_out pll6_ou t[3..0] pll11_out pll5_out[3..0] pll5_fb pll6_fb g lo ba l c lo c k s reg ion a l c lo c k s reg ion a l c lo c k s (1) ( 2 ) (1) ( 2 ) ( 2 ) ( 2 ) (1) (1) altera corporation 2?87 july 2005 stratix device handbook, volume 1 stratix architecture enhanced plls stratix devices contain up to four enhanced plls with advanced clock management features. figure 2?52 shows a diagram of the enhanced pll. figure 2?52. stratix enhanced pll notes to figure 2?52 : (1) external feedback is available in plls 5 and 6. (2) this single-ended external output is available from the g 0 counter for plls 11 and 12. (3) these four counters and external outputs are available in plls 5 and 6. (4) this connection is only available on ep1s40 and larger st ratix devices. for example, plls 5 and 11 are adjacent and plls 6 and 12 are adjacent. the ep1s40 device in the 780-pin fineline bga package does not support plls 11 and 12. /n char g e pump vco / g 0 / g 1 / g 2 /e0 8 4 g lo ba l c lo c k s /e1 /e2 i/ o b u ffers (3) /e3 t t t t t t t t lock detect to i/o buffers or g eneral routin g inclk0 inclk1 fbin pfd / g 3 /l1 /l0 from adjacent pll /m spread spectrum i/o buffers ( 2 ) (1) loop filter & filter pr o grammab l e ti me de l a y on e ac h p ll p o rt p o st - sca l e c oun ters clock switch-over circuitry p h ase f re qu e n c y detect o r v co p h ase se l ect ion se l ectab l e at e ac h p ll o u tp u t p o rt v co p h ase se l ect ion a ffect in g all o u tp u ts t t t t reg ion a l c lo c k s 4 2?88 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks clock multiplication & division each stratix device enhanced pll provides clock synthesis for pll output ports using m /( n post-scale counter) scaling factors. the input clock is divided by a pre-scale divider, n , and is then multiplied by the m feedback factor. the control loop drives the vco to match f in ( m / n ). each output port has a unique post-scale counter that divides down the high-frequency vco. for multiple pll outputs with different frequencies, the vco is set to the least common multiple of the output frequencies that meets its frequency specifications. then, the post-scale dividers scale down the output frequency for each output port. for example, if output frequencies required from one pll are 33 and 66 mhz, set the vco to 330 mhz (the least comm on multiple in the vco?s range). there is one pre-scale counter, n , and one multiply counter, m , per pll, with a range of 1 to 512 on each. there are two post-scale counters ( l ) for regional clock output po rts, four counters ( g ) for global clock output ports, and up to four counters ( e ) for external clock outputs, all ranging from 1 to 1024 with a 50% duty cycle setting. the post-scale counters range from 1 to 512 with any non-50% duty cycle setting. the quartus ii software automatically chooses the a ppropriate scaling factors according to the input frequency, multiplication, and division values entered. clock switchover to effectively develop high-reliability network systems, clocking schemes must support multiple clocks to provide redundancy. for this reason, stratix device enhanced plls support a flexible clock switchover capability. figure 2?53 shows a block diagram of the switchover circuit.the switchover circuit is co nfigurable, so you can define how to implement it. clock-sense circuitry automatically switches from the primary to secondary clock for pll reference when the primary clock signal is not present. altera corporation 2?89 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?53. clock switchover circuitry there are two possible ways to use the clock switchover feature. use automatic switchover circuitry for switching between inputs of the same frequency. for example, in applications that require a redundant clock with the same freq uency as the primary clock, the switchover state machine generates a signal that controls the multiplexer select in put on the bottom of figure 2?53 . in this case, the secondary clock becomes the reference clock for the pll. use the clkswitch input for user- or system-controlled switch conditions. this is possible for same-frequency switchover or to switch between inputs of different frequencies. for example, if inclk0 is 66 mhz and inclk1 is 100 mhz, you must control the switchover because the automatic clock-sense circuitry cannot monitor primary and secondary clock frequencies with a frequency difference of more than 20%. th is feature is us eful when clock sources can originate from multi ple cards on the backplane, requiring a system-controlled swit chover between frequencies of operation. you can use clkswitch together with the lock signal to trigger the switch from a clock that is running but becomes unstable and cannot be locked onto. n counter clkloss inclk0 inclk1 clk1_bad clk0_bad clkswitch pfd fbclk clock sense smclksw enhanced pll active clock switch-over state machine t muxout 2?90 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks during switchover, the pll vco cont inues to run and will either slow down or speed up, generating freque ncy drift on the pll outputs. the clock switchover transiti ons without any glitches. after the switch, there is a finite resynchronization period to lock onto new clock as the vco ramps up. the exact amount of time it takes for the pll to relock relates to the pll configuration and ma y be adjusted by using the programmable bandwidth feature of th e pll. the specification for the maximum time to relock is 100 s. f for more information on clock switchover, see an 313, implementing clock switchover in stra tix & stratix gx devices . pll reconfiguration the pll reconfiguration feature enables system logic to change stratix device enhanced pll counters and delay elements without reloading a programmer object file ( .pof ). this provides considerable flexibility for frequency synthesis, allowing real-t ime pll frequency and output clock delay variation. you can sweep the pll output frequencies and clock delay in prototype environments. th e pll reconfiguration feature can also dynamically or intelligently control system clock speeds or t co delays in end systems. clock delay elements at each pll outp ut port implement variable delay. figure 2?54 shows a diagram of the overall dynamic pll control feature for the counters and the clock delay elements. the config uration time is less than 20 s for the enhanced pll using a input shift clock rate of 22 mhz. the charge pump, loop filt er components, and phase shifting using vco phase taps cannot be dynamically adjusted. altera corporation 2?91 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?54. dynamically program mable counters & delays in stratix device enhanced plls pll reconfiguration data is shifted into serial registers from the logic array or external devices. the pll input shift data uses a reference input shift clock. once the last bit of the se rial chain is clocked in, the register chain is synchronously loaded into the pll configuration bits. the shift circuitry also provides an asynchronous clear for the serial registers. f for more information on pll reconfiguration, see an 282: implementing pll reconfiguration in stratix & stratix gx devices. programmable bandwidth you have advanced control of the pll bandwidth using the programmable control of the pll loop characteristics, including loop filter and charge pump. the pll?s bandwidth is a measure of its ability to track the input clock and jitter. a high-bandwidth pll can quickly lock onto a reference clock and react to any changes in th e clock. it also will allow a wide band of input jitter spectrum to pass to the output. a low- bandwidth pll will take longer to lock, but it will attenuate all high- frequency jitter components. the quartus ii software can adjust pll characteristics to achieve the de sired bandwidth. the programmable n t t m g t l t e t pfd vco char g e pump loop filter f ref scandata scanclk scanaclr c oun ters a n d c lo c k de l a y sett in gs are pr o grammab l e all o u tp u t c oun ters a n d c lo c k de l a y sett in gs ca n be pr o grammed d yn am i ca lly 2?92 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks bandwidth is tuned by varying the ch arge pump current, loop filter resistor value, high frequency capacitor value, and m counter value. you can manually adjust these values if desired. bandwidth is programmable from 200 khz to 1.5 mhz. external clock outputs enhanced plls 5 and 6 each support up to eight single-ended clock outputs (or four differential pairs). differential sstl and hstl outputs are implemented using 2 single-e nded output buffers which are programmed to have opposite polarity . in quartus ii software, simply assign the appropriate differential i/o standard and the software will implement the inversion. see figure 2?55 . altera corporation 2?93 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?55. external clock outputs for plls 5 & 6 notes to figure 2?55 : (1) the design can use each external clock output pin as a general-purpose output pin from the logic array. these pins are multiplexed with ioe outputs. (2) two single-ended outputs ar e possible per output counter ? either two outputs of the same frequency and phase or one shifted 180 . (3) ep1s10, ep1s20, and ep1s25 devices in 672-pin bga and 484- and 672-pin fineline bga packages only have two pairs of external clocks (i.e., pll_out0p , pll_out0n , pll_out1p , and pll_out1n ). (4) differential sstl and hstl outputs are implemente d using two single-ended ou tput buffers, which are programmed to have opposite polarity. e 0 counter pll_out0p (3) , (4 ) pll_out0n (3) , (4 ) pll_out1p (3) , (4 ) pll_out1n (3) , (4 ) pll_out2p (3) , (4 ) pll_out2n (3) , (4 ) pll_out3p (3) , (4 ) pll_out3n (3) , (4 ) e 1 counter e 2 counter e 3 counter from ioe (1) , ( 2 ) from ioe (1) from ioe (1) from ioe (1) from ioe (1) from ioe (1) from ioe (1) from ioe (1) 4 (3) 2?94 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks any of the four external output coun ters can drive the single-ended or differential clock outputs for plls 5 and 6. this means one counter or frequency can drive all output pins available from pll 5 or pll 6. each pair of output pins (four pins total) has dedicated vcc and gnd pins to reduce the output clock?s overall ji tter by providing im proved isolation from switching i/o pins. for plls 5 and 6, each pi n of a single-ended output pair can either be in phase or 180 out of phase. the clock output pin pairs support the same i/o standards as standard output pins (in the top and bottom banks) as well as lvds, lvpecl, 3.3-v pcml, hypertransport technology, differential hstl, and differential sstl. table 2?20 shows which i/o standards the enhanced pll clock pins support. when in single-ended or differential mode, the two outputs operate off the same power supply. both outputs use the same standards in single-ended mode to maintain performance. you can also use the ex ternal clock output pins as user output pins if external enhanc ed pll clocking is not needed. table 2?20. i/o standards supported for enhanced pll pins (part 1 of 2) i/o standard input output inclk fbin pllenable extclk lv t t l vv v v lv c m o s vv v v 2.5 v vv v 1.8 v vv v 1.5 v vv v 3.3-v pci vv v 3.3-v pci-x 1.0 vv v lvpecl vv v 3.3-v pcml vv v lv d s vv v hypertransport technology vv v differential hstl vv differential sstl v 3.3-v gtl vv v 3.3-v gtl+ vv v 1.5-v hstl class i vv v altera corporation 2?95 july 2005 stratix device handbook, volume 1 stratix architecture enhanced plls 11 and 12 support one single-ended output each (see figure 2?56 ). these outputs do not have their own vcc and gnd signals. therefore, to minimize jitter, do not place switching i/o pins next to this output pin. figure 2?56. external clock outputs for enhanced plls 11 & 12 note to figure 2?56 : (1) for pll 11, this pin is clk13n ; for pll 12 this pin is clk7n . stratix devices can drive any enhanc ed pll driven through the global clock or regional clock network to an y general i/o pin as an external output clock. the jitter on the output clock is not guaranteed for these cases. 1.5-v hstl class ii vv v 1.8-v hstl class i vv v 1.8-v hstl class ii vv v sstl-18 class i vv v sstl-18 class ii vv v sstl-2 class i vv v sstl-2 class ii vv v sstl-3 class i vv v sstl-3 class ii vv v agp (1 and 2 ) vv v ctt vv v table 2?20. i/o standards supported for enhanced pll pins (part 2 of 2) i/o standard input output inclk fbin pllenable extclk clk13n, i/o, pll11_out or clk6n, i/o, pll12_out (1 ) from internal logic or ioe g 0 counter 2?96 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks clock feedback the following four feedback modes in stratix device enhanced plls allow multiplication and/or phase and delay shifting: zero delay buffer: the external cl ock output pin is phase-aligned with the clock input pin for zero de lay. altera recommends using the same i/o standard on the input clock and the output clocks for optimum performance. external feedback: the exte rnal feedback input pin, fbin , is phase- aligned with the clock input, clk , pin. aligning these clocks allows you to remove clock delay and skew between devices. this mode is only possible for plls 5 and 6. pl ls 5 and 6 each support feedback for one of the dedicated external ou tputs, either one single-ended or one differential pair . in this mode, one e counter feeds back to the pll fbin input, becoming part of the feedback loop. altera recommends using the same i/o st andard on the input clock, the fbin pin, and the output clocks for optimum performance. normal mode: if an internal clock is used in this mode, it is phase- aligned to the input cloc k pin. the external cl ock output pin will have a phase delay relative to the clock input pin if connected in this mode. you define which internal clock output from the pll should be phase-aligned to th e internal clock pin. no compensation: in this mode, th e pll will not compensate for any clock networks or external clock outputs. phase & delay shifting stratix device enhanced plls prov ide advanced prog rammable phase and clock delay shifting. these para meters are set in the quartus ii software. phase delay the quartus ii software automatically sets the phase taps and counter settings according to the phase shift en try. you enter a desired phase shift and the quartus ii software automa tically sets the closest setting achievable. this type of phase shift is not reconfigurable during system operation. for phase shifting, enter a phase shift (in degrees or time units) for each pll clock output port or for all outputs together in one shift. you can select phase-shifting values in time units with a resolution of 156.25 to 416.66 ps. this resolution is a fu nction of frequency input and the multiplication and division factors (tha t is, it is a function of the vco period), with the finest step being equal to an eighth (0.125) of the vco period. each clock output counter ca n choose a different phase of the altera corporation 2?97 july 2005 stratix device handbook, volume 1 stratix architecture vco period from up to eight taps for individual fine step selection. also, each clock output counter can use a unique initial count setting to achieve individual coarse shift selection in steps of one vco period. the combination of coarse and fine shifts allows phase shifting for the entire input clock period. the equation to determin e the precision of the ph ase shifting in degrees is: 45 post-scale counter value. therefore, the maximum step size is 45 , and smaller steps are possible depending on the multiplication and division ratio necessary on the output counter port. this type of phase shift provides the highest precision since it is the least sensitive to process, supply, and temperature variation. clock delay in addition to the phase shift featur e, the ability to fine tune the t clock delay provides advanced time delay sh ift control on each of the four pll outputs. there are time delays for each post-scale counter ( e , g , or l ) from the pll, the n counter, and m counter. each of these can shift in 250-ps increments for a range of 3.0 ns. the m delay shifts all outputs earlier in time, while n delay shifts all outputs later in time. individual delays on post-scale counters ( e , g , and l ) provide positive delay for each output. table 2?21 shows the combined delay for ea ch output for normal or zero delay buffer mode where t e , t g , or t l is unique for each pll output. the t output for a single output can range from ?3 ns to +6 ns. the total delay shift difference between any two pll outputs, however, must be less than 3 ns. for example, shifts on tw o outputs of ?1 and +2 ns is allowed, but not ?1 and +2.5 ns beca use these shifts would result in a difference of 3.5 ns. if the design uses external feedback, the t e delay will remove delay from outputs, repr esented by a negative sign (see table 2?21 ). this effect occurs because the t e delay is then part of the feedback loop. table 2?21. output clock delay for enhanced plls normal or zero delay buffer mode external feedback mode t e output = t n ? t m + t e t g output = t n ? t m + t g t l output = t n ? t m + t l t e output = t n ? t m ? t e (1) t g output = t n ? t m + t g t l output = t n ? t m + t l note to table 2?21 : (1) t e removes delay from outputs in external feedback mode. 2?98 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks the variation due to process, volt age, and temperature is about 15 % on the delay settings. pll reconfiguration can control the clock delay shift elements, but not the vco phase sh ift multiplexers, during system operation. spread-spectrum clocking stratix device enhanced plls use spread-spectrum technology to reduce electromagnetic interference generation from a syst em by distributing the energy over a broader frequency range. the enhanced pll typically provides 0.5% down spread modulation using a triangular profile. the modulation frequency is programmable. enabling spread-spectrum for a pll affects all of its outputs. lock detect the lock output indicates that there is a stable clock output signal in phase with the reference clock. withou t any additional ci rcuitry, the lock signal may toggle as the pll begins tr acking the reference clock. you may need to gate the lock signal for use as a system control. the lock signal from the locked port can drive the logic array or an output pin. whenever the pll loses lock (for example, inclk jitter, clock switchover, pll reconfiguration, power supply noise, and so on), the pll must be reset with the areset signal to guarantee correct phase relationship between the pll output clocks. if the phase relationship between the input clock versus output clock, and between different output clocks from the pll is not important in th e design, then the pll need not be reset. f see the stratix fpga errata sheet for more information on implementing the gated lock signal in a design. programmable duty cycle the programmable duty cycle allows enhanced plls to generate clock outputs with a variable duty cycle. this featur e is supported on each enhanced pll post-scale counter ( g 0.. g 3, l 0.. l 3, e 0.. e 3). the duty cycle setting is achieved by a low and high time count setting for the post-scale dividers. the quartus ii software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices. advanced clear & enable control there are several control signals for cl earing and enabling plls and their outputs. you can use these signals to control pll resynchronization and gate pll output clocks for low-power applications. altera corporation 2?99 july 2005 stratix device handbook, volume 1 stratix architecture the pllenable pin is a dedicated pin that enables/disables plls. when the pllenable pin is low, the clock ou tput ports are driven by gnd and all the plls go out of lock. when the pllenable pin goes high again, the plls relock and resynchronize to th e input clocks. you can choose which plls are controlled by the pllenable signal by connecting the pllenable input port of the altpll megafunction to the common pllenable input pin. the areset signals are reset/re synchronization inputs for each pll. the areset signal should be asserted ev ery time the pll loses lock to guarantee correct phase relationship between the pll output clocks. users should include the areset signal in designs if any of the following conditions are true: pll reconfiguration or clock switchover enables in the design. phase relationships between output clocks need to be maintained after a loss of lock condition the device input pins or logic el ements (les) can drive these input signals. when driven high, the pll counters will reset, clearing the pll output and placing the pll out of lock. the vco will set back to its nominal setting (~700 mhz). when dr iven low again, the pll will resynchronize to its input as it relock s. if the target vco frequency is below this nominal frequency, then th e output frequency will start at a higher value than desired as the pll locks. if the system cannot tolerate this, the clkena signal can disable the output clocks until the pll locks. the pfdena signals control the phase frequency detector (pfd) output with a programmable gate. if you disa ble the pfd, the vco operates at its last set value of control voltage and frequency with some long-term drift to a lower frequency. the system continues running when the pll goes out of lock or the input clock is disabled. by maintaining the last locked frequency, the system has time to store its current settings before shutting down. you can either us e your own control signal or a clkloss status signal to trigger pfdena . the clkena signals control the enhanced pll regional and global outputs. each regional and global output port has its own clkena signal. the clkena signals synchronously disable or enable the clock at the pll output port by gating the outputs of the g and l counters. the clkena signals are registered on the falling edge of the counter output clock to enable or disable the clock without glitches. figure 2?57 shows the waveform example for a pll clock port enable. the pll can remain locked independent of the clkena signals since the loop-related counters are not affected. this feature is useful for applications that require a low power or sleep mode. upon re-enabling, the pll does not need a 2?100 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks resynchronization or relock period. the clkena signal can also disable clock outputs if the system is not to lerant to frequency overshoot during resynchronization. the extclkena signals work in the same way as the clkena signals, but they control the external clock output counters ( e 0, e 1, e 2, and e 3). upon re-enabling, the pll does not need a resynchronization or relock period unless the pll is using external feedback mode. in order to lock in external feedback mode, the external output must drive the board trace back to the fbin pin. figure 2?57. extclkena signals fast plls stratix devices contain up to eight fast plls with high-speed serial interfacing ability, along with general-purpose features. figure 2?58 shows a diagram of the fast pll. counter output clkena clkout altera corporation 2?101 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?58. stratix device fast pll notes to figure 2?58 : (1) the global or regional clock input can be driven by an output from another pll or any dedicated clk or fclk pin. it cannot be driven by intern ally-generated global signals. (2) in high-speed differential i/o support mode, this high-s peed pll clock feeds the serdes. stratix devices only support one rate of data transfer per fast p ll in high-speed differential i/o support mode. (3) this signal is a high-speed differential i/o support serdes control signal. clock multiplication & division stratix device fast plls provide clock synthesis for pll output ports using m /(post scaler) scaling factors. the input clock is multiplied by the m feedback factor. each output port has a unique post scale counter to divide down the high-frequency vco. there is one multiply divider, m , per fast pll with a range of 1 to 32. there are two post scale l dividers for regional and/or lvds interface clocks, and g 0 counter for global clock output port; all range from 1 to 32. in the case of a high-speed differential interface, set the output counter to 1 to allow the high-speed vco frequency to drive the serdes. when used for clocking the serdes, the m counter can range from 1 to 30. the vco frequency is equal to f in m, where vco frequency must be between 300 and 1000 mhz. char g e pump vco g 0 8 clock input pfd l 1 l 0 m loop filter p h ase f re qu e n c y detect o r v co p h ase se l ect ion se l ectab l e at eac h p ll o u tp u t p o rt p o st - sca l e c oun ters global or re g ional cloc k global or re g ional cloc k global or re g ional cloc k diffioclk2 ( 2 ) diffioclk1 ( 2 ) txload_en (3) rxload_en (3) global or re g ional clock (1) 2?102 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks external clock inputs each fast pll supports single-ended or differential inputs for source synchronous transmitters or fo r general-purpose use. source- synchronous receivers support differential clock inputs. the fast pll inputs are fed by clk[0..3] , clk[8..11] , and fpll[7..10]clk pins, as shown in figure 2?50 on page 2?85 . table 2?22 shows the i/o standards supported by fast pll input pins. table 2?22. fast pll port i/o standards (part 1 of 2) i/o standard input inclk pllenable lv t t l vv lv c m o s vv 2.5 v v 1.8 v v 1.5 v v 3.3-v pci 3.3-v pci-x 1.0 lvpecl v 3.3-v pcml v lv d s v hypertransport technology v differential hstl v differential sstl 3.3-v gtl 3.3-v gtl+ v 1.5-v hstl class i v 1.5-v hstl class ii 1.8-v hstl class i v 1.8-v hstl class ii sstl-18 class i v sstl-18 class ii sstl-2 class i v altera corporation 2?103 july 2005 stratix device handbook, volume 1 stratix architecture table 2?23 shows the performance on each of the fast pl l clock inputs when using lvds, lvpecl, 3.3-v pcml , or hypertransport technology. external clock outputs each fast pll supports differential or single-ended outputs for source- synchronous transmitters or for gene ral-purpose external clocks. there are no dedicated external clock outp ut pins. any i/o pi n can be driven by the fast pll global or regional outputs as an external output pin. the i/o standards supported by any pa rticular bank determines what standards are possible for an external clock output driven by the fast pll in that bank. phase shifting stratix device fast plls have advanced clock shift capability that enables programmable phase shifts. you can enter a phase shift (in degrees or time units) for each pll clock output port or for all outputs together in one shift. you can perform phase shifti ng in time units with a resolution range of 125 to 416.66 ps. this resolution is a function of the vco period, with the finest step being equal to an eighth (0.125) of the vco period. sstl-2 class ii v sstl-3 class i v sstl-3 class ii v agp (1 and 2 ) ctt v table 2?23. lvds performance on fast pll input fast pll clock input maxim um input frequency (mhz) clk0, clk2, clk9, clk11, fpll7clk, fpll8clk, fpll9clk, fpll10clk 717 (1) clk1, clk3, clk8, clk10 645 note to table 2?23 : (1) see the chapter dc & switching characteristics of the stratix device handbook, volume 1 for more information. table 2?22. fast pll port i/o standards (part 2 of 2) i/o standard input inclk pllenable 2?104 altera corporation stratix device handbook, volume 1 july 2005 i/o structure control signals the fast pll has the same lock output, pllenable input, and areset input control signals as the enhanced pll. if the input clock stops and causes the pll to lose lock, then the pll must be reset for correct phase shift operation. for more information on high-speed differential i/o support, see ?high- speed differential i/o support? on page 2?130 . i/o structure ioes provide many features, including: dedicated differential and single-ended i/o buffers 3.3-v, 64-bit, 66-mhz pci compliance 3.3-v, 64-bit, 133-mhz pci-x 1.0 compliance joint test action group (jtag) boundary-scan test (bst) support differential on-chip termination for lvds i/o standard programmable pull-up during configuration output drive strength control slew-rate control tri-state buffers bus-hold circuitry programmable pull-up resistors programmable input and output delays open-drain outputs dq and dqs i/o pins double-data rate (ddr) registers the ioe in stratix devices contains a bidirectional i/o buffer, six registers, and a latch for a complete embedded bidirectional single data rate or ddr transfer. figure 2?59 shows the stratix ioe structure. the ioe contains two input registers (plus a latch), two output registers, and two output enable registers. the desi gn can use both input registers and the latch to capture ddr input and both output registers to drive ddr outputs. additionally, the design can use the output enable (oe) register for fast clock-to-output enable timi ng. the negative edge-clocked oe register is used for ddr sdram interfacing. the quartus ii software automatically duplicates a single oe register that controls multiple output or bidirectional pins. altera corporation 2?105 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?59. stratix ioe structure the ioes are located in i/o blocks around the periphery of the stratix device. there are up to four ioes per row i/o block and six ioes per column i/o block. the row i/o blocks drive row, column, or direct link interconnects. the column i/o blocks drive column interconnects. figure 2?60 shows how a row i/o block connects to the logic array. figure 2?61 shows how a column i/o bloc k connects to th e logic array. dq output register output a dq output register output b input a input b dq oe register oe dq oe register dq input register dq input register dq input latch logic array clk ena 2?106 altera corporation stratix device handbook, volume 1 july 2005 i/o structure figure 2?60. row i/o block c onnection to the interconnect notes to figure 2?60 : (1) the 16 control signals are composed of four output enables io_boe[3..0] , four clock enables io_bce[3..0] , four clocks io_clk[3..0] , and four clear signals io_bclr[3..0] . (2) the 28 data and control signals consist of eight data out lines: four lines each for ddr applications io_dataouta[3..0] and io_dataoutb[3..0] , four output enables io_coe[3..0] , four input clock enables io_cce_in[3..0] , four output clock enables io_cce_out[3..0] , four clocks io_cclk[3..0] , and four clear signals io_cclr[3..0] . 16 28 r4, r8 & r24 interconnects c4, c8 & c16 interconnects i/o block local interconnect 16 control signals from i/o interconnect (1) i/o interconnect 28 data & control signals from logic array (2) io_dataouta[3..0] io_dataoutb[3..0] io_clk[7:0] horizontal i/o block contains up to four ioes direct link interconnect to adjacent lab direct link interconnect to adjacent lab lab local interconnect lab horizontal i/o block altera corporation 2?107 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?61. column i/o block connection to the interconnect notes to figure 2?61 : (1) the 16 control signals are composed of four output enables io_boe[3..0] , four clock enables io_bce[3..0] , four clocks io_bclk[3..0] , and four clear signals io_bclr[3..0] . (2) the 42 data and control signals consist of 12 data out lines; six lines each for ddr applications io_dataouta[5..0] and io_dataoutb[5..0] , six output enables io_coe[5..0] , six input clock enables io_cce_in[5..0] , six output clock enables io_cce_out[5..0] , six clocks io_cclk[5..0] , and six clear signals io_cclr[5..0] . 16 control signals from i/o interconnect (1) 42 data & control signals from logic array (2) vertical i/o block contains up to six ioes i/o block local interconnect i/o interconnec t io_datain[ 3 : 0 ] r4, r8 & r24 interconnects lab local interconnect c4, c8 & c16 interconnects 16 42 lab lab lab io_clk[7..0] vertical i/o block 2?108 altera corporation stratix device handbook, volume 1 july 2005 i/o structure stratix devices have an i/o interc onnect similar to the r4 and c4 interconnect to drive high-fanout si gnals to and from the i/o blocks. there are 16 signals that drive into the i/o bloc ks composed of four output enables io_boe[3..0] , four clock enables io_bce[3..0] , four clocks io_bclk[3..0] , and four clear signals io_bclr[3..0] . the pin?s datain signals can drive the io interconnect, which in turn drives the logic array or other i/o blocks. in addition, the control and data signals can be driven from the logic array, providing a slower but more flexible routing resource. the row or column ioe clocks, io_clk[7..0] , provide a dedicated routing resource for low-skew, high-speed clocks. i/o clocks are generated from regional, global, or fast regional clocks (see ?plls & clock networks? on page 2?73 ). figure 2?62 illustrates the signal paths through the i/o block. figure 2?62. signal path through the i/o block row or column io_clk[7..0] io_boe[3..0] io_bce[3..0] io_bclk[3..0] io_bclr[3..0] io_datain0 io_datain1 io_dataout0 io_dataout1 io_coe oe ce_in ce_out io_cce_in aclr/apreset io_cce_out sclr/spreset io_cclr clk_in io_cclk clk_out control signal selection ioe from i/o interconnect to logic array from logic array to other ioes altera corporation 2?109 july 2005 stratix device handbook, volume 1 stratix architecture each ioe contains its own control signal selection for the following control signals: oe , ce_in , ce_out , aclr/preset , sclr/preset , clk_in , and clk_out . figure 2?63 illustrates the control signal selection. figure 2?63. control signal selection per ioe in normal bidirectional operation, the input register can be used for input data requiring fast setup times. the input register can have its own clock input and clock enable separate from the oe and output registers. the output register can be used for da ta requiring fast clock-to-output performance. the oe register can be used for fast clock-to-output enable timing. the oe and output register share the same clock source and the same clock enable source from local interconnect in the associated lab, dedicated i/o clocks, and the column and row interconnects. figure 2?64 shows the ioe in bidirectional configuration. clk_out ce_in clk_in ce_out aclr/preset sclr/preset i/o interconnect [15..0] dedicated i/o clock [7..0] local interconnect local interconnect local interconnect local interconnect local interconnect oe io_coe io_cclr io_cce_out io_cce_in io_cclk io_bclk[3..0] io_bce[3..0] io_bclr[3..0] io_boe[3..0] 2?110 altera corporation stratix device handbook, volume 1 july 2005 i/o structure figure 2?64. stratix ioe in bidi rectional i/o configuration note (1) note to figure 2?64 : (1) all input signals to the io e can be inverted at the ioe. the stratix device ioe includes programmable delays that can be activated to ensure zero hold time s, input ioe register-to-logic array register transfers, or logic array-to-output ioe register transfers. a path in which a pin directly drives a register may require the delay to ensure zero hold time, whereas a path in which a pin drives a register through combinatorial logic may not require the delay. programmable delays exist for decreasing input-pin-to-logic-array and ioe input register delays. the quartus ii comp iler can program these delays to automatically mini mize setup time while prov iding a zero hold time. programmable delays can increase the register-to-pin delays for output clrn/prn dq ena chip-wide reset oe register clrn/prn dq ena output register v ccio v ccio optional pci clamp programmable pull-up resistor column or row interconnect i/o interconnect [15..0] ioe_clk[7..0] bus-hold circuit output enable clock enable delay output clock enable delay logic array to output register delay output t zx delay oe register t co delay clrn/prn dq ena input register input clock enable delay input pin to input register delay input pin to logic array delay drive strength control open-drain output slew control sclr/preset oe clkout ce_out aclr/prn clkin ce_in output pin delay altera corporation 2?111 july 2005 stratix device handbook, volume 1 stratix architecture and/or output enable registers. a programmable delay exists to increase the t zx delay to the output pin, which is required for zbt interfaces. table 2?24 shows the programmable delays for stratix devices. the ioe registers in stratix devices share the same source for clear or preset. you can program preset or clea r for each individual ioe. you can also program the registers to power up high or low after configuration is complete. if programmed to power up low, an asynchronous clear can control the registers. if programmed to power up high, an asynchronous preset can control the registers. this feature prevents the inadvertent activation of another device?s acti ve-low input upon power-up. if one register in an ioe uses a preset or clear signal then all registers in the ioe must use that same signal if they require preset or clear. additionally a synchronous reset signal is available for the ioe registers. double-data rate i/o pins stratix devices have six registers in the ioe, which support ddr interfacing by clocking data on both positive and negative clock edges. the ioes in stratix devices support ddr inputs, ddr outputs, and bidirectional ddr modes. when using the ioe for ddr inputs, th e two input registers clock double rate input data on alternating edges. an input latch is also used within the ioe for ddr input acquisition. the la tch holds the data that is present during the clock high times. this allows both bits of data to be synchronous with the same clock ed ge (either rising or falling). figure 2?65 shows an ioe configured for ddr input. figure 2?66 shows the ddr input ti ming diagram. table 2?24. stratix programmable delay chain programmable delays quartus ii logic option input pin to logic array delay decreas e input delay to internal cells input pin to input register delay de crease input delay to input register output pin delay increase delay to output pin output enable register t co delay increase delay to output enable pin output t zx delay increase t zx delay to output pin output clock enable delay increase output clock enable delay input clock enable delay increase input clock enable delay logic array to output register delay de crease input delay to output register output enable clock enable delay increase output enable clock enable delay 2?112 altera corporation stratix device handbook, volume 1 july 2005 i/o structure figure 2?65. stratix ioe in dd r input i/o configuration note (1) notes to figure 2?65 : (1) all input signals to the io e can be inverted at the ioe. (2) this signal connection is only al lowed on dedicated dq function pins. (3) this signal is for dedicated dqs function pins only. clrn/prn dq ena chip-wide reset input register clrn/prn dq ena input register vccio vccio optional pci clamp programmable pull-up resistor column or row interconnect i/o interconnect [15..0] dqs local bus (1), (2) to dqs local bus (3) ioe_clk[7..0] bus-hold circuit output clock enable delay clrn/prn dq ena latch input pin to input register delay sclr clkin aclr/prn (1) (1) altera corporation 2?113 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?66. input timing diagram in ddr mode when using the ioe for ddr output s, the two output registers are configured to clock two data paths from les on rising clock edges. these output registers are multiplexed by the clock to drive the output pin at a 2 rate. one output register clocks th e first bit out on th e clock high time, while the other output register clocks the second bit out on the clock low time. figure 2?67 shows the ioe configured for ddr output. figure 2?68 shows the ddr output timing diagram. data at input pin a' b' clk a0 b1 a1 a1 b2 a2 a3 a2 a3 b1 b2 b3 b3 b4 input to logic array 2?114 altera corporation stratix device handbook, volume 1 july 2005 i/o structure figure 2?67. stratix ioe in ddr output i/o configuration notes (1) , (2) notes to figure 2?67 : (1) all input signals to the io e can be inverted at the ioe. (2) the tristate is by default active high. it can, however, be designed to be active low. clrn/prn dq ena chip-wide reset oe register clrn/prn dq ena oe register clrn/prn dq ena output register v ccio v ccio optional pci clamp programmabl e pull-up resistor column or row interconnect i/o interconnect [15..0] ioe_clk[7..0] bus-hold circuit logic array to output register delay output t zx delay oe register t co delay clrn/prn dq ena output register logic array to output register delay drive strength control open-drain output slew control used for ddr sdram clk sclr aclr/prn clkout output pin delay output enable clock enable delay output clock enable delay altera corporation 2?115 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?68. output timing diagram in ddr mode the stratix ioe operates in bidire ctional ddr mode by combining the ddr input and ddr output configur ations. stratix device i/o pins transfer data on a ddr bidirectional bus to support ddr sdram. the negative-edge-clocked oe register hold s the oe signal inactive until the falling edge of the clock. this is done to meet ddr sdram timing requirements. external ram interfacing stratix devices support ddr sdram at up to 200 mhz (400-mbps data rate) through dedicated phase-shift circuitry, qdr and qdrii sram interfaces up to 167 mhz, and zbt sram interfaces up to 200 mhz. stratix devices also provide preliminary support for reduced latency dram ii (rldram ii) at rates up to 200 mhz through the dedicated phase-shift circuitry. 1 in addition to the required si gnals for external memory interfacing, stratix de vices offer the optional clock enable signal. by default the quartus ii software sets the clock enable signal high, which tells the output regi ster to update with new values. the output registers ho ld their own values if the design sets the clock enable signal low. see figure 2?64 . f to find out more about the ddr sd ram specification, see the jedec web site ( www.jedec.org ). for information on memory controller megafunctions for stratix device s, see the altera web site ( www.altera.com ). see an 342: interfacing ddr sdram with stratix & stratix gx devices for more information on ddr sdram interface in stratix. also see an 349: qdr sram controller reference design for stratix & stratix gx devices and an 329: zbt sram controller reference design for stratix & stratix gx devices . f r o m in ter n a l reg i sters ddr output clk a b b1 a1 b2 a2 b3 a3 a2 a1 a3 a4 b1 b2 b3 b4 2?116 altera corporation stratix device handbook, volume 1 july 2005 i/o structure tables 2?25 and 2?26 show the performance specification for ddr sdram, rldram ii, qdr sram, qdrii sram, and zbt sram interfaces in ep1s10 through ep1s 40 devices and in ep1s60 and ep1s80 devices. the ddr sdram and qdr sram numbers in table 2?25 have been verified with hardware char acterization with third-party ddr sdram and qdr sram devices over temperature and voltage extremes. table 2?25. external ram support in ep1s10 through ep1s40 devices ddr memory type i/o standard maximum clock rate (mhz) -5 speed grade -6 speed grade -7 speed grade -8 speed grade flip-chip flip-chip wire- bond flip- chip wire- bond flip- chip wire- bond ddr sdram (1) , (2) sstl-2 200 167 133 133 100 100 100 ddr sdram - side banks (2) , (3) , (4) sstl-2 150 133 110 133 100 100 100 rldram ii (4) 1.8-v hstl 200 (5) (5) (5) (5) (5) (5) qdr sram (6) 1.5-v hstl 167 167 133 133 100 100 100 qdrii sram (6) 1.5-v hstl 200 167 133 133 100 100 100 zbt sram (7) lvttl 200 200 200 167 167 133 133 notes to table 2?25 : (1) these maximum clock rates apply if the stratix device uses dqs phase-shift circuit ry to interface with ddr sdram. dqs phase-shift circuitry is only available in the top and bottom i/o banks (i/o banks 3, 4, 7, and 8). (2) for more informati on on ddr sdram, see an 342: interfacing ddr sdram wi th stratix & stratix gx devices. (3) ddr sdram is supported on the strati x device side i/o banks (i/o banks 1, 2, 5, and 6) without dedicated dqs phase-shift circuitry. the read dqs signal is ignored in this mode. (4) these performance specifications are preliminary. (5) this device does not support rldram ii. (6) for more information on qdr or qdrii sram, see an 349: q dr sram controller reference design for stratix & stratix gx devices . (7) for more informati on on zbt sram, see an 329: zbt sram controller reference design for stratix & stratix gx devices . altera corporation 2?117 july 2005 stratix device handbook, volume 1 stratix architecture in addition to six i/o registers and one input latch in the ioe for interfacing to these high-speed memory interfaces, stratix devices also have dedicated circuitry for interfacing with ddr sdram. in every stratix device, the i/o banks at the top (i/o banks 3 and 4) and bottom (i/o banks 7 and 8) of the device support ddr sdram up to 200 mhz. these pins support dqs signals with dq bus modes of 8, 16, or 32. table 2?27 shows the number of dq and dqs buses that are supported per device. table 2?26. external ram support in ep1s60 & ep1s80 devices ddr memory type i/o standard maximum clock rate (mhz) -5 speed grade -6 speed grade -7 speed grade ddr sdram (1) , (2) sstl-2 167 167 133 ddr sdram - side banks (2) , (3) sstl-2 150 133 133 qdr sram (4) 1.5-v hstl 133 133 133 qdrii sram (4) 1.5-v hstl 167 167 133 zbt sram (5) lvttl 200 200 167 notes to table 2?26 : (1) these maximum clock rates apply if the stratix device uses dqs phase-shift circuit ry to interface with ddr sdram. dqs phase-shift circuitry is only available in the top and bottom i/o banks (i/o banks 3, 4, 7, and 8). (2) for more informati on on ddr sdram, see an 342: interfacing ddr sdram wi th stratix & stratix gx devices. (3) ddr sdram is supported on the strati x device side i/o banks (i/o banks 1, 2, 5, and 6) without dedicated dqs phase-shift circuitry. the read dqs signal is ignored in this mode. numbers are preliminary. (4) for more information on qdr or qdrii sram, see an 349: q dr sram controller reference design for stratix & stratix gx devices . (5) for more informati on on zbt sram, see an 329: zbt sram controller reference design for stratix & stratix gx devices . table 2?27. dqs & dq bus mode support (part 1 of 2) note (1) device package number of 8 groups number of 16 groups number of 32 groups ep1s10 672-pin bga 672-pin fineline bga 12 (2) 00 484-pin fineline bga 780-pin fineline bga 16 (3) 04 ep1s20 484-pin fineline bga 18 (4) 7 (5) 4 672-pin bga 672-pin fineline bga 16 (3) 7 (5) 4 780-pin fineline bga 20 7 (5) 4 2?118 altera corporation stratix device handbook, volume 1 july 2005 i/o structure a compensated delay element on ea ch dqs pin automatically aligns input dqs synchronization signals with the data window of their corresponding dq data signals. the dqs signals drive a local dqs bus in the top and bottom i/o banks. this dq s bus is an additional resource to the i/o clocks and is used to cloc k dq input registers with the dqs signal. two separate single phase-shifting reference circuits are located on the top and bottom of the stratix device. each circuit is driven by a system reference clock through the clk pins that is the same frequency as the dqs signal. clock pins clk[15..12]p feed the phase-shift circuitry on the top of the device and clock pins clk[7..4]p feed the phase-shift circuitry on the bottom of the device . the phase-shifting reference circuit on the top of the device controls th e compensated delay elements for all 10 dqs pins located at the top of the device. the phase-shifting reference circuit on the bottom of the device controls the compensated delay elements for all 10 dqs pins locate d on the bottom of the device. all 10 delay elements (dqs signals) on ei ther the top or bottom of the device ep1s25 672-pin bga 672-pin fineline bga 16 (3) 84 780-pin fineline bga 1,020-pin fineline bga 20 8 4 ep1s30 956-pin bga 780-pin fineline bga 1,020-pin fineline bga 20 8 4 ep1s40 956-pin bga 1,020-pin fineline bga 1,508-pin fineline bga 20 8 4 ep1s60 956-pin bga 1,020-pin fineline bga 1,508-pin fineline bga 20 8 4 ep1s80 956-pin bga 1,508-pin fineline bga 1,923-pin fineline bga 20 8 4 notes to table 2?27 : (1) see the selectable i/o standards in stratix & stratix gx devices chapter in the stratix device handbook, volume 2 for v ref guidelines. (2) these packages have six groups in i/o banks 3 and 4 and six groups in i/o banks 7 and 8. (3) these packages have eight grou ps in i/o banks 3 and 4 and eigh t groups in i/o banks 7 and 8. (4) this package has nine groups in i/o banks 3 and 4 and nine groups in i/o banks 7 and 8. (5) these packages have three groups in i/o banks 3 and 4 and four groups in i/o banks 7 and 8. table 2?27. dqs & dq bus mode support (part 2 of 2) note (1) device package number of 8 groups number of 16 groups number of 32 groups altera corporation 2?119 july 2005 stratix device handbook, volume 1 stratix architecture shift by the same degree amount. for example, all 10 dqs pins on the top of the device can be shifted by 90 an d all 10 dqs pins on the bottom of the device can be shifted by 72. the reference circuits require a maximum of 256 system reference clock cycles to set the correct phase on the dqs delay elements. figure 2?69 illustrates the phase-shift reference circuit control of each dqs delay shift on the top of the device. this same circuit is duplicated on the bottom of the device. figure 2?69. simplified diagram of the dqs phase-shift circuitry see the external memory interfaces chapter in the stratix device handbook , volume 2 for more information on ex ternal memory interfaces. programmable drive strength the output buffer for each stratix device i/o pin has a programmable drive strength control for certain i/o standards. the lvttl and lvcmos standard has several levels of drive strength that the user can control. sstl-3 class i and ii, sstl-2 class i and ii, hstl class i and ii, and 3.3-v gtl+ support a minimum setting, the lowest drive strength that guarantees the i oh /i ol of the standard. using minimum settings provides signal slew rate control to reduce system noise and signal overshoot. phase comparator up/down counter delay chains input reference clock control signals to dqs pins 6 2?120 altera corporation stratix device handbook, volume 1 july 2005 i/o structure table 2?28 shows the possible settings fo r the i/o standards with drive strength control. quartus ii software version 4.2 and la ter will report current strength as ?pci compliant? for 3.3-v pci, 3. 3-v pci-x 1.0, and compact pci i/o standards. stratix devices support series on-chip termination (oct) using programmable drive strength. for more information, contact your altera support representative. open-drain output stratix devices provide an optional open-drain (equivalent to an open- collector) output for each i/o pin. this open-drain output enables the device to provide system-level control signals (e.g., interrupt and write- enable signals) that can be asse rted by any of several devices. slew-rate control the output buffer for each stratix device i/o pin has a programmable output slew-rate control that can be configured for low-noise or high- speed performance. a faster slew rate provides high-speed transitions for high-performance systems. howeve r, these fast transitions may introduce noise transien ts into the system. a slow slew rate reduces system noise, but adds a nominal delay to rising and falling edges. each table 2?28. programmable drive strength i/o standard i oh / i ol current strength setting (ma) 3.3-v lvttl 24 (1) , 16, 12, 8, 4 3.3-v lvcmos 24 (2) , 12 (1) , 8, 4, 2 2.5-v lvttl/lvcmos 16 (1) , 12, 8, 2 1.8-v lvttl/lvcmos 12 (1) , 8, 2 1.5-v lvcmos 8 (1) , 4, 2 gtl/gtl+ 1.5-v hstl class i and ii 1.8-v hstl class i and ii sstl-3 class i and ii sstl-2 class i and ii sstl-18 class i and ii support max and min strength notes to ta b l e 2 ? 2 8 : (1) this is the quartus ii soft ware default current setting. (2) i/o banks 1, 2, 5, and 6 do not support this setting. altera corporation 2?121 july 2005 stratix device handbook, volume 1 stratix architecture i/o pin has an individual slew-rate control, allowing you to specify the slew rate on a pin-by-pin basis. the slew-rate control affects both the rising and falling edges. bus hold each stratix device i/o pin provides an optional bus-hold feature. the bus-hold circuitry can weakly hold the signal on an i/o pin at its last- driven state. since the bus-hold feature holds the last-driven state of the pin until the next input si gnal is present, an exte rnal pull-up or pull-down resistor is not needed to hold a sign al level when the bus is tri-stated. table 2?29 shows bus hold support for different pin types. the bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. you can select this featur e individually for each i/o pin. the bus-hold output drives no higher than v ccio to prevent overdriving signals. if the bus-hold feature is enabled, the programmable pull-up option cannot be used. disable the bus-hold feature when using open- drain outputs with the gtl+ i/o standard or when the i/o pin has been configured for differential signals. the bus-hold circuitry uses a resistor with a nominal resistance (r bh ) of approximately 7 k to weakly pull the signal level to the last-driven state. see the dc & switching characteristics chapter of the stratix device handbook, volume 1 for the specific sustaining current driven through this resistor and overdrive current used to identify the next-driven input level. this information is provided for each v ccio voltage level. the bus-hold circuitry is active only after configuration. when going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. table 2?29. bus hold support pin type bus hold i/o pins v clk[15..0] clk[0,1,2,3,8,9,10,11] fclk v fpll[7..10]clk 2?122 altera corporation stratix device handbook, volume 1 july 2005 i/o structure programmable pull-up resistor each stratix device i/o pin provides an optional programmable pull-up resistor during user mode. if this feature is enabled for an i/o pin, the pull-up resistor (typically 25 k ) weakly holds the output to the v ccio level of the output pin?s bank. table 2?30 shows which pin types support the weak pull-up resistor feature. advanced i/o standard support stratix device ioes support the following i/o standards: lvttl lvcmos 1.5 v 1.8 v 2.5 v 3.3-v pci 3.3-v pci-x 1.0 3.3-v agp (1 and 2) lvds lvpecl 3.3-v pcml hypertransport differential hstl (on input/output clocks only) differential sstl (on output column clock pins only) gtl/gtl+ 1.5-v hstl class i and ii table 2?30. programmable weak pull-up resistor support pin type programmable w eak pull-up resistor i/o pins v clk[15..0] fclk v fpll[7..10]clk configuration pins jtag pins v (1) note to table 2?30 : (1) tdo pins do not support programmable weak pull-up resistors. altera corporation 2?123 july 2005 stratix device handbook, volume 1 stratix architecture 1.8-v hstl class i and ii sstl-3 class i and ii sstl-2 class i and ii sstl-18 class i and ii ctt table 2?31 describes the i/o standards supported by stratix devices. table 2?31. stratix supported i/o standards i/o standard type input reference voltage (v ref ) (v) output supply voltage (v ccio ) (v) board termination voltage (v tt ) (v) lvttl single-ended n/a 3.3 n/a lvcmos single-ended n/a 3.3 n/a 2.5 v single-ended n/a 2.5 n/a 1.8 v single-ended n/a 1.8 n/a 1.5 v single-ended n/a 1.5 n/a 3.3-v pci single-ended n/a 3.3 n/a 3.3-v pci-x 1.0 single-ended n/a 3.3 n/a lvds differential n/a 3.3 n/a lvpecl differential n/a 3.3 n/a 3.3-v pcml differential n/a 3.3 n/a hypertransport differential n/a 2.5 n/a differential hstl (1) differential 0.75 1.5 0.75 differential sstl (2) differential 1.25 2.5 1.25 gtl voltage-referenced 0.8 n/a 1.20 gtl+ voltage-referenced 1.0 n/a 1.5 1.5-v hstl class i and ii voltage-referenced 0.75 1.5 0.75 1.8-v hstl class i and ii voltage-referenced 0.9 1.8 0.9 sstl-18 class i and ii voltage-referenced 0.90 1.8 0.90 sstl-2 class i and ii voltage-referenced 1.25 2.5 1.25 sstl-3 class i and ii voltage-referenced 1.5 3.3 1.5 agp (1 and 2 ) voltage-referenced 1.32 3.3 n/a ctt voltage-referenced 1.5 3.3 1.5 notes to table 2?31 : (1) this i/o standard is only availa ble on input and output clock pins. (2) this i/o standard is only avai lable on output column clock pins. 2?124 altera corporation stratix device handbook, volume 1 july 2005 i/o structure f for more information on i/o standard s supported by stratix devices, see the selectable i/o standards in stratix & stratix gx devices chapter of the stratix device handbook, volume 2 . stratix devices contain eight i/o banks in addition to the four enhanced pll external clock out banks, as shown in figure 2?70 . the four i/o banks on the right and left of the de vice contain circui try to support high- speed differential i/o for lvds, lvpecl, 3.3-v pcml, and hypertransport inputs and output s. these banks support all i/o standards listed in table 2?31 except pci i/o pins or pci-x 1.0, gtl, sstl-18 class ii, and hstl class ii outputs. the top and bottom i/o banks support all single-ended i/o standards. additionally, stratix devices support four enhanced pll external clock output banks, allowing clock output capabilities su ch as differential support for sstl and hstl. table 2?32 shows i/o standard support for each i/o bank. altera corporation 2?125 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?70. strati x i/o banks notes (1) , (2) , (3) notes to figure 2?70 : (1) figure 2?70 is a top view of the silicon die. this will correspond to a top-down view for non-flip-chip packages, but will be a reverse view for flip-chip packages. (2) figure 2?70 is a graphic representation only. se e the device pin-outs on the web ( www.altera.com ) and the quartus ii software for exact locations. (3) banks 9 through 12 are enhanced pll external clock output banks. (4) if the high-speed differential i/o pins are not used for high-speed differential signaling, they can support all of the i/o standards except hs tl class i and ii, gtl, sstl-18 cl ass ii, pci, pci-x 1.0, and agp 1 /2 . (5) for guidelines for placing single-ended i/o pads next to differential i/o pads, see the selectable i/o standards in stratix and stratix gx devices chapter in the stratix device handbook, volume 2 . lv ds, lv p e c l , 3.3-v pcm l , a n d hy per t ra n sp o rt i/ o b lo c k a n d reg ul ar i/ o p in s (4) lv ds, lv p e c l , 3.3-v pcm l , a n d hy per t ra n sp o rt i/ o b lo c k a n d reg ul ar i/ o p in s (4) i/ o ba nk s 3 , 4 , 9 & 10 s u pp o rt all s in g l e -en ded i/ o sta n dards i/ o ba nk s 7 , 8, 11 & 1 2 s u pp o rt all s in g l e -en ded i/ o sta n dards i/ o ba nk s 1 , 2, 5, a n d 6 s u pp o rt all s in g l e -en ded i/ o sta n dards ex cept d i ffere n t i a l h s tl o u tp u t c lo c k s, d i ffere n t i a l ss tl- 2 o u tp u t c lo c k s, h s tl c l ass ii , g tl , ss tl-1 8 c l ass ii , pc i , pc i-x 1.0 , a n d a gp 1 / 2 dqs9t dqs8t dqs7t dqs6t dqs5t dqs4t dqs3t dqs2t dqs1t dqs0t pll5 vref1b3 vref2b3 vref3b3 vref4b3 vref5b3 vref1b4 vref2b4 vref3b4 vref4b4 vref5b4 vref5b8 vref4b8 vref3b8 vref2b8 vref1b8 vref5b7 vref4b7 vref3b7 vref2b7 vref1b7 pll6 dqs9b dqs8b dqs7b dqs6b dqs5b dqs4b dqs3b dqs2b dqs1b dqs0b 910 vref1b2 vref2b2 vref3b2 vref4b2 vref1b1 vref2b1 vref3b1 vref4b1 vref4b6 vref3b6 vref2b6 vref1b6 vref4b5 vref3b5 vref2b5 vref1b5 bank 5 bank 6 pll3 pll4 pll1 pll2 bank 1 bank 2 bank 3 bank 4 11 12 bank 8 bank 7 lv ds, lv p e c l , 3.3-v pcm l , a n d hy per t ra n sp o rt i/ o b lo c k a n d reg ul ar i/ o p in s (4) lv ds, lv p e c l , 3.3-v pcm l , a n d hy per t ra n sp o rt i/ o b lo c k a n d reg ul ar i/ o p in s (4) pll7 pll10 pll8 pll9 pll12 pll11 ( 5 ) ( 5 ) ( 5 ) ( 5 ) 2?126 altera corporation stratix device handbook, volume 1 july 2005 i/o structure table 2?32 shows i/o standard support for each i/o bank. table 2?32. i/o support by bank (part 1 of 2) i/o standard top & bottom banks (3, 4, 7 & 8) left & right banks (1, 2, 5 & 6) enhanced pll external clock output banks (9, 10, 11 & 12) lv t t l vvv lv c m o s vvv 2.5 v vvv 1.8 v vvv 1.5 v vvv 3.3-v pci vv 3.3-v pci-x 1.0 vv lvpecl vv 3.3-v pcml vv lv d s vv hypertransport technology vv differential hstl (clock inputs) vv differential hstl (clock outputs) v differential sstl (clock outputs) v 3.3-v gtl vv 3.3-v gtl+ vvv 1.5-v hstl class i vvv 1.5-v hstl class ii vv 1.8-v hstl class i vvv 1.8-v hstl class ii vv sstl-18 class i vvv sstl-18 class ii vv sstl-2 class i vvv sstl-2 class ii vvv sstl-3 class i vvv altera corporation 2?127 july 2005 stratix device handbook, volume 1 stratix architecture each i/o bank has its own vccio pins. a single device can support 1.5-, 1.8-, 2.5-, and 3.3-v interfaces; each bank can support a different standard independently. each ba nk also has dedicated vref pins to support any one of the voltage-referenced standa rds (such as sstl-3) independently. each i/o bank can support multiple standards with the same v ccio for input and output pins. each bank can support one voltage-referenced i/o standard. for example, when v ccio is 3.3 v, a bank can support lvttl, lvcmos, 3.3-v pci, and sstl-3 for inputs and outputs. differential on-chip termination stratix devices provide differenti al on-chip termination (lvds i/o standard) to reduce reflections and main tain signal integrity. differential on-chip termination simplifies board design by minimizing the number of external termination resistors re quired. termination can be placed inside the package, eliminating sm all stubs that can still lead to reflections. the internal termination is designed using transistors in the linear region of operation. stratix devices support internal diff erential termination with a nominal resistance value of 137.5 for lvds input receiver buffers. lvpecl signals require an external termination resistor. figure 2?71 shows the device with differential termination. sstl-3 class ii vvv agp (1 and 2 ) vv ctt vvv table 2?32. i/o support by bank (part 2 of 2) i/o standard top & bottom banks (3, 4, 7 & 8) left & right banks (1, 2, 5 & 6) enhanced pll external clock output banks (9, 10, 11 & 12) 2?128 altera corporation stratix device handbook, volume 1 july 2005 i/o structure figure 2?71. lvds input differ ential on-chip termination i/o banks on the left and right side of the device support lvds receiver (far-end) differential termination. table 2?33 shows the stratix device differential termination support. table 2?34 shows the termination support for different pin types. the differential on-chip resistance at the receiver input buffer is 118 20 %. r d + e + e transmittin g device receivin g device with differential termination z 0 z 0 table 2?33. differential terminat ion supported by i/o banks differential termination support i/o standard support top & bottom banks (3, 4, 7 & 8) left & right banks (1,2,5 & 6) differential termination (1) , (2) lv d s v notes to table 2?33 : (1) clock pin clk0 , clk2 , clk9 , clk11 , and pins fpll[7..10]clk do not support differential termination. (2) differential termination is only su pported for lvds because of a 3.3-v v ccio . table 2?34. differential termination support across pin types pin type r d top and bottom i/o banks (3, 4, 7, and 8) diffio_rx[] v clk[0,2,9,11],clk[4-7],clk[12-15] clk[1,3,8,10] v fclk fpll[7..10]clk altera corporation 2?129 july 2005 stratix device handbook, volume 1 stratix architecture however, there is additional resistan ce present between the device ball and the input of the receiver buffer, as shown in figure 2?72 . this resistance is because of package trace resistance (which can be calculated as the resistance from the package ball to the pad) and the parasitic layout metal routing resistance (which is shown between the pad and the intersection of the on-chip termination and input buffer). figure 2?72. differential resistance of lvds differential pin pair ( r d ) table 2?35 defines the specification for internal termination resistance for commercial devices. multivolt i/o interface the stratix architecture supports th e multivolt i/o interface feature, which allows stratix devices in all pa ckages to interface with systems of different supply voltages. the stratix vccint pins must always be co nnected to a 1.5-v power supply. with a 1.5-v v ccint level, input pins are 1.5-v, 1.8-v, 2.5-v, and 3.3-v tolerant. the vccio pins can be connected to either a 1.5-v, 1.8-v, 2.5-v, or 3.3-v power supply, depe nding on the output requirements. lvds input buffer differential on-chip termination resisto r 9.3 9.3 0.3 0.3 r d pad package ball table 2?35. differential on-chip termination symbol description conditions resistance unit min typ max r d (2) internal differential termination for lvds commercial (1) , (3) 110 135 165 w industrial (2) , (3) 100 135 170 w notes to table 2?35 : (1) data measured over minimum conditions (t j = 0 c, v ccio +5%) and maximum conditions (t j = 85 c, v ccio =?5%). (2) data measured over minimum conditions (t j = ?40 c, v ccio +5%) and maximum conditions (t j = 100 c, v ccio =?5%). (3) lvds data rate is supported for 840 mbps using internal differential termination. 2?130 altera corporation stratix device handbook, volume 1 july 2005 high-speed differential i/o support the output levels are compatible with systems of the same voltage as the power supply (i.e., when vccio pins are connected to a 1.5-v power supply, the output levels are comp atible with 1.5-v systems). when vccio pins are connected to a 3.3-v po wer supply, the output high is 3.3 v and is compatible with 3.3-v or 5.0-v systems. table 2?36 summarizes stratix multivolt i/o support. high-speed differential i/o support stratix devices contain dedicated circuitry for supporting differential standards at speeds up to 840 mbps. the following differential i/o standards are supported in the stratix device: lvds, lvpecl, hypertransport, and 3.3-v pcml. there are four dedicated high-spe ed plls in the ep1s10 to ep1s25 devices and eight dedicated high-speed plls in the ep1s30 to ep1s80 devices to multiply reference clocks and drive high-speed differential serdes channels. f see the stratix device pin-outs at www.altera.com for additional high speed diffio pin informat ion for stratix devices. table 2?36. stratix mu ltivolt i/o support note (1) v ccio (v) input signal (5) output signal (6) 1.5 v1.8 v2.5 v3.3 v5.0 v1.5 v1.8 v2.5 v3.3 v5.0 v 1.5 vv v (2) v (2) v 1.8 v (2) v v (2) v (2) v (3) v 2.5 vv v (3) v (3) v 3.3 v (2) v v (4) v (3) v (3) v (3) vv notes to table 2?36 : (1) to drive inputs higher than v ccio but less than 4.1 v, disable the pci clamping diode. however, to drive 5.0-v inputs to the device, enable the pci clamping diode to prevent v i from rising above 4.0 v. (2) the input pin current may be slightly higher than the typical value. (3) although v ccio specifies the voltage necessary for the stratix devi ce to drive out, a receiving device powered at a different level can still interface with the strati x device if it has inputs that tolerate the v ccio value. (4) stratix devices can be 5.0-v tolerant with the use of an external resistor and the internal pci clamp diode. (5) this is the external signal th at is driving the stratix device. (6) this represents the system voltage th at stratix supports when a vccio pin is connected to a specific voltage level. for example, when vccio is 3.3 v and if the i/o standa rd is lvttl/lvcmos, the ou tput high of the signal coming out from stratix is 3.3 v and is compatible with 3.3-v or 5.0-v systems. altera corporation 2?131 july 2005 stratix device handbook, volume 1 stratix architecture table 2?37 shows the number of channels that each fast pll can clock in ep1s10, ep1s20, and ep1s25 devices. tables 2?38 through table 2?41 show this information for ep1s30, ep1s40, ep1s60, an d ep1s80 devices. table 2?37. ep1s10, ep1s20 & ep1s25 device differential channels (part 1 of 2) note (1) device package transmitter/ receiver total channels maximum speed (mbps) center fast plls pll 1 pll 2 pll 3 pll 4 ep1s10 484-pin fineline bga transmitter (2) 20 840 (4) 5555 840 (3) 10 10 10 10 receiver 20 840 (4) 5555 840 (3) 10 10 10 10 672-pin fineline bga 672-pin bga transmitter (2) 36 624 (4) 9999 624 (3) 18 18 18 18 receiver 36 624 (4) 9999 624 (3) 18 18 18 18 780-pin fineline bga transmitter (2) 44 840 (4) 11 11 11 11 840 (3) 22 22 22 22 receiver 44 840 (4) 11 11 11 11 840 (3) 22 22 22 22 ep1s20 484-pin fineline bga transmitter (2) 24 840 (4) 6666 840 (3) 12 12 12 12 receiver 20 840 (4) 5555 840 (3) 10 10 10 10 672-pin fineline bga 672-pin bga transmitter (2) 48 624 (4) 12 12 12 12 624 (3) 24 24 24 24 receiver 50 624 (4) 13 12 12 13 624 (3) 25 25 25 25 780-pin fineline bga transmitter (2) 66 840 (4) 17 16 16 17 840 (3) 33 33 33 33 receiver 66 840 (4) 17 16 16 17 840 (3) 33 33 33 33 2?132 altera corporation stratix device handbook, volume 1 july 2005 high-speed differential i/o support when you span two i/o banks using cross-bank support, you can route only two load enable signals total between the plls. when you enable rx_data_align , you use both rxloadena and txloadena of a pll. that leaves no loadena for the second pll. ep1s25 672-pin fineline bga 672-pin bga transmitter (2) 56 624 (4) 14 14 14 14 624 (3) 28 28 28 28 receiver 58 624 (4) 14 15 15 14 624 (3) 29 29 29 29 780-pin fineline bga transmitter (2) 70 840 (4) 18 17 17 18 840 (3) 35 35 35 35 receiver 66 840 (4) 17 16 16 17 840 (3) 33 33 33 33 1,020-pin fineline bga transmitter (2) 78 840 (4) 19 20 20 19 840 (3) 39 39 39 39 receiver 78 840 (4) 19 20 20 19 840 (3) 39 39 39 39 notes to table 2?37 : (1) the first row for each transmitter or receiver reports the number of channels driven directly by the pll. the second row below it shows the maximum channels a pll can drive if cross bank channels are us ed from the adjacent center pll. for example, in the 484-pin fineline bga ep1s10 device, pll 1 can drive a maximum of five channels at 840 mbps or a maximum of 10 channels at 840 mbps. th e quartus ii software may also merge receiver and transmitter plls when a receiver is dri ving a transmitter. in this case, on e fast pll can drive both the maximum numbers of receiver and transmitter channels. (2) the number of channels listed in cludes the transmitter clock output ( tx_outclock ) channel. if the design requires a ddr clock, it can use an extra data channel. (3) these channels span across two i/o banks per side of the device. when a center pll clocks channels in the opposite bank on the same side of the device it is called cro ss-bank pll support. both center plls can clock cross-bank channels simultaneously if, for example, pll_1 is clocking all receiver channels and pll_2 is clocking all transmitter channels. you cannot have two adjacent plls simultaneously clocki ng cross-bank receiver channels or two adjacent plls simultaneously cloc king transmitter channels. cross-bank allows for all receiver channels on one side of the device to be clocked on one clock while all transmitter channe ls on the device are clocked on the other center pll. crossbank plls are supported at full-spee d, 840 mbps. for wire-bond devices, the full-speed is 624 mbps. (4) these values show the channels available for each pll without crossing another bank. table 2?37. ep1s10, ep1s20 & ep1s25 device differential channels (part 2 of 2) note (1) device package transmitter/ receiver total channels maximum speed (mbps) center fast plls pll 1 pll 2 pll 3 pll 4 altera corporation 2?133 july 2005 stratix device handbook, volume 1 stratix architecture the only way you can use the rx_data_align is if one of the following is true: the receiver pll is only clocking receive channels (no resources for the transmitter) if all channels can fit in one i/o bank table 2?38. ep1s30 differential channels note (1) package transmitter /receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) , (3) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 780-pin fineline bga transmitter (4) 70 840 18 17 17 18 (6) (6) (6) (6) 840 (5) 35 35 35 35 (6) (6) (6) (6) receiver 66 840 17 16 16 17 (6) (6) (6) (6) 840 (5) 33 33 33 33 (6) (6) (6) (6) 956-pin bga transmitter (4) 80 840 19 20 20 19 20 20 20 20 840 (5) 39 39 39 39 20 20 20 20 receiver 80 840 20 20 20 20 19 20 20 19 840 (5) 40 40 40 40 19 20 20 19 1,020-pin fineline bga transmitter (4) 80 (2) (7) 840 19 (1) 20 20 19 (1) 20 20 20 20 840 (5) , (8) 39 (1) 39 (1) 39 (1) 39 (1) 20 20 20 20 receiver 80 (2) (7) 840 20 20 20 20 19 (1) 20 20 19 (1) 840 (5) , (8) 40 40 40 40 19 (1) 20 20 19 (1) table 2?39. ep1s40 differential channels (part 1 of 2) note (1) package transmitter/ receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) , (3) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 780-pin fineline bga transmitter (4) 68 840 18 16 16 18 (6) (6) (6) (6) 840 (5) 34 34 34 34 (6) (6) (6) (6) receiver 66 840 17 16 16 17 (6) (6) (6) (6) 840 (5) 33 33 33 33 (6) (6) (6) (6) 2?134 altera corporation stratix device handbook, volume 1 july 2005 high-speed differential i/o support 956-pin bga transmitter (4) 80 840 18 17 17 18 20 20 20 20 840 (5) 35 35 35 35 20 20 20 20 receiver 80 840 20 20 20 20 18 17 17 18 840 (5) 40 40 40 40 18 17 17 18 1,020-pin fineline bga transmitter (4) 80 (10) (7) 840 18 (2) 17 (3) 17 (3) 18 (2) 20 20 20 20 840 (5) , (8) 35 (5) 35 (5) 35 (5) 35 (5) 20 20 20 20 receiver 80 (10) (7) 840 20 20 20 20 18 (2) 17 (3) 17 (3) 18 (2) 840 (5) , (8) 40 40 40 40 18 (2) 17 (3) 17 (3) 18 (2) 1,508-pin fineline bga transmitter (4) 80 (10) (7) 840 18 (2) 17 (3) 17 (3) 18 (2) 20 20 20 20 840 (5) , (8) 35 (5) 35 (5) 35 (5) 35 (5) 20 20 20 20 receiver 80 (10) (7) 840 20 20 20 20 18 (2) 17 (3) 17 (3) 18 (2) 840 (5) , (8) 40 40 40 40 18 (2) 17 (3) 17 (3) 18 (2) table 2?40. ep1s60 differential channels (part 1 of 2) note (1) package transmitter/ receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) , (3) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 956-pin bga transmitter (4) 80 840 12 10 10 12 20 20 20 20 840 (5) , (8) 22 22 22 22 20 20 20 20 receiver 80 840 20 20 20 20 12 10 10 12 840 (5) , (8) 40 40 40 40 12 10 10 12 table 2?39. ep1s40 differential channels (part 2 of 2) note (1) package transmitter/ receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) , (3) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 altera corporation 2?135 july 2005 stratix device handbook, volume 1 stratix architecture 1,020-pin fineline bga transmitter (4) 80 (12) (7) 840 12 (2) 10 (4) 10 (4) 12 (2) 20 20 20 20 840 (5) , (8) 22 (6) 22 (6) 22 (6) 22 (6) 20 20 20 20 receiver 80 (10) (7) 840 20 20 20 20 12 (8) 10 (10) 10 (10) 12 (8) 840 (5) , (8) 40 40 40 40 12 (8) 10 (10) 10 (10) 12 (8) 1,508-pin fineline bga transmitter (4) 80 (36) (7) 840 12 (8) 10 (10) 10 (10) 12 (8) 20 20 20 20 840 (5) , (8) 22 (18) 22 (18) 22 (18) 22 (18) 20 20 20 20 receiver 80 (36) (7) 840 20 20 20 20 12 (8) 10 (10) 10 (10) 12 (8) 840 (5) , (8) 40 40 40 40 12 (8) 10 (10) 10 (10) 12 (8) table 2?41. ep1s80 differential channels (part 1 of 2) note (1) package transmitter/ receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) , (3) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 956-pin bga transmitter (4) 80 (40) (7) 840 10 10 10 10 20 20 20 20 840 (5) , (8) 20 20 20 20 20 20 20 20 receiver 80 840 20 20 20 20 10 10 10 10 840 (5) , (8) 40 40 40 40 10 10 10 10 1,020-pin fineline bga transmitter (4) 92 (12) (7) 840 10 (2) 10 (4) 10 (4) 10 (2) 20 20 20 20 840 (5) , (8) 20 (6) 20 (6) 20 (6) 20 (6) 20 20 20 20 receiver 90 (10) (7) 840 20 20 20 20 10 (2) 10 (3) 10 (3) 10 (2) 840 (5) , (8) 40 40 40 40 10 (2) 10 (3) 10 (3) 10 (2) table 2?40. ep1s60 differential channels (part 2 of 2) note (1) package transmitter/ receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) , (3) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 2?136 altera corporation stratix device handbook, volume 1 july 2005 high-speed differential i/o support 1,508-pin fineline bga transmitter (4) 80 (72) (7) 840 10 (10) 10 (10) 10 (10) 10 (10) 20 (8) 20 (8) 20 (8) 20 (8) 840 (5) , (8) 20 (20) 20 (20) 20 (20) 20 (20) 20 (8) 20 (8) 20 (8) 20 (8) receiver 80 (56) (7) 840 20 20 20 20 10 (14) 10 (14) 10 (14) 10 (14) 840 (5) , (8) 40 40 40 40 10 (14) 10 (14) 10 (14) 10 (14) notes to tables 2?38 through 2?41 : (1) the first row for each transmitter or receiver reports the number of channels driven directly by the pll. the second row below it shows the maximum channels a pll can drive if cross bank channels are used from the adjacent center pll. for example, in the 780-pin fineline bga ep1s 30 device, pll 1 can drive a maximum of 18 transmitter channels at 840 mbps or a maximum of 35 transmitter channels at 840 mbps. the quartus ii software may also merge transmitter and receiver plls wh en a receiver is driving a transmitter. in this case, on e fast pll can drive both the maximum numbers of rece iver and trans mitter channels. (2) some of the channels accessible by the center fast pll an d the channels accessible by th e corner fast pll overlap. therefore, the total number of channels is not the addition of the n umber of channels accessible by plls 1, 2, 3, and 4 with the number of channels accessible by plls 7, 8, 9, and 10. for more information on which channels overlap, see the stratix device pin-outs at www.altera.com . (3) the corner fast plls in this device support a data rate of 840 mbps for channels labeled ?high? speed in the device pin-outs at www.altera.com . (4) the numbers of channels listed in clude the transmitter clock output ( tx_outclock ) channel. an extra data channel can be used if a ddr clock is needed. (5) these channels span across two i/o banks per side of the device. when a center pll clocks channels in the opposite bank on the same side of the device it is called cro ss-bank pll support. both center plls can clock cross-bank channels simultaneously if say pll_1 is clocking all receiver channels and pll_2 is clocking all transmitter channels. you cannot have two adjace nt plls simultaneously clocking cr oss-bank receiver channels or two adjacent plls simultaneously clocking transmitter channels. cross-bank allows for all receiver channels on one side of the device to be clocked on one clock while all transmitter channels on the device are clocked on the other center pll. crossbank plls are supported at full-speed, 840 mbps. for wire-bond devices, the full-speed is 624 mbps. (6) plls 7, 8, 9, and 10 are not available in this device. (7) the number in parentheses is the n umber of slow-speed channels, guaranteed to operate at up to 462 mbps. these channels are independent of the high-sp eed differential channels. for the location of these channels, see the device pin-outs at www.altera.com . (8) see the stratix device pin-outs at www.altera.com . channels marked ?high? spee d are 840 mbps and ?low? speed channels are 462 mbps. table 2?41. ep1s80 differential channels (part 2 of 2) note (1) package transmitter/ receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) , (3) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 altera corporation 2?137 july 2005 stratix device handbook, volume 1 stratix architecture the high-speed differential i/o ci rcuitry supports the following high speed i/o interconnect standards and applications: utopia iv spi-4 phase 2 (pos-phy level 4) sfi-4 10g ethernet xsbi rapidio hypertransport dedicated circuitry stratix devices support source-synchronous interfacing with lvds, lvpecl, 3.3-v pcml, or hypertrans port signaling at up to 840 mbps. stratix devices can transmit or receive serial channels along with a low-speed or high-speed clock. the receiving device pll multiplies the clock by a integer factor w (w = 1 through 32). for example, a hypertransport applicat ion where the data rate is 800 mbps and the clock rate is 400 mhz would require that w be set to 2. the serdes factor j determines the parallel data width to deserialize from receivers or to serialize for transmitters. the serdes fa ctor j can be set to 4, 7, 8, or 10 and does not have to equal the pll clock-multiplication w value. for a j factor of 1, the stratix device bypasses the serdes block. for a j factor of 2, the stratix device bypasses the serdes block, and the ddr input and output registers are used in the ioe. see figure 2?73 . figure 2?73. high-speed differential i/o rece iver / transmitter interface example + ? 8 data data fast pll 105 mhz 8 840 mbps ded i cated rece iv er in terface ded i cated t ra n sm i tter in terface r 4 , r8, a n d r2 4 in terc onn ect lo ca l in terc onn ect 8 + ? 8 840 mbps tx_load_en rx_load_en re g ional or g lobal cloc k 8 2?138 altera corporation stratix device handbook, volume 1 july 2005 high-speed differential i/o support an external pin or global or regional clock can drive the fast plls, which can output up to three clocks: two mu ltiplied high-speed differential i/o clocks to drive the serdes block and/or external pin, and a low-speed clock to drive the logic array. the quartus ii megawizard ? plug-in manager only allows the implementation of up to 20 receiver or 20 transmitter channels for each fast pll. these channels operate at up to 840 mbps. the receiver and transmitter channels are in terleaved such that each i/o bank on the left and right side of the device has one receiver channel and one transmitter channel per lab row. figure 2?74 shows the fast pll and channel layout in ep1s10, ep1s20, and ep1s25 devices. figure 2?75 shows the fast pll and channel layout in th e ep1s30 to ep1s80 devices. figure 2?74. fast pll & channel layout in the ep1s10, ep1s20 or ep1s25 devices note (1) notes to figure 2?74 : (1) wire-bond packages support up to 624 mbps. (2) see table 2?41 for the number of channels each device supports. (3) there is a multiplexer here to select the pll clock source. if a pll uses this multiplexer to clock channels outside of its bank quadrant, those clocked channels support up to 840 mbps for ?high? speed channels and 462 mbps for ?low? speed channels, as labele d in the device pin-outs at www.altera.com . transmitter receiver transmitter receiver clkin clkin transmitter receiver transmitter receiver clkin clkin fast pll 1 fast pll 2 ( 3 ) fast pll 4 fast pll 3 ( 3 ) up to 2 0 receiver and transmitter channels (2) up to 2 0 receiver and transmitter channels (2) up to 2 0 receiver and transmitter channels (2) up to 2 0 receiver and transmitter channels (2) altera corporation 2?139 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?75. fast pll & channel layout in the ep1s30 to ep1s80 devices note (1) notes to figure 2?75 : (1) wire-bond packages support up to 624 mbps. (2) see table 2?38 through 2?41 for the number of channe ls each device supports. (3) there is a multiplexer here to select the pll clock source. if a pll uses this multiplexer to clock channels outside of its bank quadrant, those clocked channels support up to 840 mbps for ?high? speed channels and 462 mbps for ?low? speed channels as labeled in the device pin-outs at www.altera.com . transmitter receiver transmitter receiver clkin fpll7clk transmitter receiver transmitter receiver clkin fpll10clk transmitter receiver transmitter receiver fpll9clk clkin fast pll 7 fast pll 1 up to 20 receiver and 20 transmitter channels in 20 rows (2) transmitter receiver transmitter receiver fpll8clk clkin fast pll 2 fast pll 8 up to 20 receiver and 20 transmitter channels in 20 rows (2) up to 20 receiver and 20 transmitter channels in 20 rows (2) up to 20 receiver and 20 transmitter channels in 20 rows (2) (3) (3) fast pll 10 fast pll 4 fast pll 3 fast pll 9 2?140 altera corporation stratix device handbook, volume 1 july 2005 power sequencing & hot socketing the transmitter external clock output is transmitted on a data channel. the txclk pin for each bank is located in between data transmitter pins. for 1 clocks (e.g., 622 mbps, 622 mhz), the high-speed pll clock bypasses the serdes to drive the output pins. for half-rate clocks (e.g., 622 mbps, 311 mhz) or any other even-n umbered factor such as 1/4, 1/7, 1/8, or 1/10, the serdes automatic ally generates the clock in the quartus ii software. for systems that require more than fo ur or eight high-speed differential i/o clock domains, a serdes bypass implementation is possible using ioes. byte alignment for high-speed source synchronous interfaces such as pos-phy 4, xsbi, rapidio, and hypertransport technology, the source synchronous clock rate is not a byte- or serdes-rate multiple of the data rate. byte alignment is necessary for these protocols since the source synchronous clock does not provide a byte or word boundary since the clock is one half the data rate, not one eighth. the stratix device?s high-speed differential i/o circuitry provides dedicated data realignment circuitry for user- controlled byte boundary shifting. this simplifies designs while saving le resources. an input signal to ea ch fast pll can stall deserializer parallel data outputs by one bit pe riod. you can use an le-based state machine to signal the shift of receiv er byte boundaries until a specified pattern is detected to in dicate byte alignment. power sequencing & hot socketing because stratix devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. therefore, the vccio and vccint power supplies may be powered in any order. although you can power up or down the vccio and vccint power supplies in any sequence, you shou ld not power down any i/o banks that contain configuration pins wh ile leaving other i/o banks powered on. for power up and power down, all supplies ( vccint and all vccio power planes) must be powered up and down within 100 ms of each other. this prevents i /o pins from driving out. signals can be driven into stratix devices before and during power up without damaging the device. in addi tion, stratix devices do not drive out during power up. once operating conditions are reached and the device is configured, stratix devices operate as specified by the user. for more information, see hot socketing in the selectable i/o standards in stratix & stratix gx devices chapter in the stratix device handbook, volume 2 . altera corporation 3?1 july 2005 3. configuration & testing ieee std. 1149.1 (jtag) boundary-scan support all stratix ? devices provide jtag bst circuitry that complies with the ieee std. 1149.1a-1990 spec ification. jtag boundary-scan testing can be performed either before or after, bu t not during configuration. stratix devices can also use the jtag port fo r configuration together with either the quartus ? ii software or hardware using either jam files ( .jam ) or jam byte-code files ( .jbc ). stratix devices support ioe i/o standard setting reconfiguration through the jtag bst chain. the jtag chain can update the i/o standard for all input and output pins any time before or during user mode through the config_io instruction. you can use this ability for jtag testing before configuration when some of the stratix pins drive or receive from other devices on the board using voltage-referenced standards. since the stratix device may not be configured before jtag testing, the i/o pins may not be configured for appropriate elec trical standards for chip-to-chip communication. programming those i/o standards via jtag allows you to fully test the i/o conn ection to other devices. the enhanced pll reconfig uration bits are part of the jtag chain before configuration and after power-up. after device configuration, the pll reconfiguration bits are not part of the jtag chain. the jtag pins support 1.5-v/1.8-v or 2.5-v/3.3-v i/o standards. the tdo pin voltage is determined by the v ccio of the bank where it resides. the vccsel pin selects whether the jtag inpu ts are 1.5-v, 1.8-v, 2.5-v, or 3.3-v compatible. stratix devices also use the jtag port to monitor the logic operation of the device with the signaltap ? ii embedded logic analyzer. stratix devices support the jtag instructions shown in table 3?1 . the quartus ii software has an auto usercode feature where you can choose to use the checksum value of a programming file as the jtag user code. if selected, the checksum is automatically loaded to the usercode register. in the settings dialog box in the assignments menu, click device & pin options , then general, and then turn on the auto usercode option. s51003-1.3 3?2 altera corporation stratix device handbook, volume 1 july 2005 ieee std. 1149.1 (jtag) boundary-scan support table 3?1. stratix jt ag instructions jtag instruction instr uction code description sample/preload 00 0000 0101 allows a snapshot of si gnals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. also used by the signaltap ii embedded logic analyzer. extest (1) 00 0000 0000 allows the external circui try and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. bypass 11 1111 1111 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation. usercode 00 0000 0111 selects the 32-bit usercode register and places it between the tdi and tdo pins, allowing the usercode to be serially shifted out of tdo . idcode 00 0000 0110 selects the idcode register and places it between tdi and tdo , allowing the idcode to be serially shifted out of tdo . highz (1) 00 0000 1011 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the i/o pins. clamp (1) 00 0000 1010 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices duri ng normal device operation while holding i/o pins to a state defined by the data in the boundary-scan register. icr instructions used when configuring an st ratix device via the jtag port with a masterblaster tm , byteblastermv tm , or byteblaster tm ii download cable, or when using a jam file or jam byte-code file via an embedded processor or jrunner. pulse_nconfig 00 0000 0001 emulates pulsing the nconfig pin low to trigger reconfiguration even though the physical pin is unaffected. config_io 00 0000 1101 allows configuration of i/o standards through the jtag chain for jtag testing. can be executed before, after, or during configuration. stops configuration if executed during configuration. once issued, the config_io instruction will hold nstatus low to reset the configuration device. nstatus is held low until the device is reconfigured. signaltap ii instructions monitors internal device operation with the signaltap ii embedded logic analyzer. note to ta b l e 3 ? 1 : (1) bus hold and weak pull-up resistor feat ures override the high-impedance state of highz , clamp , and extest . altera corporation 3?3 july 2005 stratix device handbook, volume 1 configuration & testing the stratix device instruction register length is 10 bits and the usercode register length is 32 bits. tables 3?2 and 3?3 show the boundary-scan register length and device idcode information for stratix devices. table 3?2. stratix boundary-scan register length device boundary-scan register length ep1s10 1,317 ep1s20 1,797 ep1s25 2,157 ep1s30 2,253 ep1s40 2,529 ep1s60 3,129 ep1s80 3,777 table 3?3. 32-bit stratix device idcode device idcode (32 bits) (1) version (4 bits) part number (16 bits) manufacturer identity (11 bits) lsb (1 bit) (2) ep1s10 0000 0010 0000 0000 0001 000 0110 1110 1 ep1s20 0000 0010 0000 0000 0010 000 0110 1110 1 ep1s25 0000 0010 0000 0000 0011 000 0110 1110 1 ep1s30 0000 0010 0000 0000 0100 000 0110 1110 1 ep1s40 0000 0010 0000 0000 0101 000 0110 1110 1 ep1s60 0000 0010 0000 0000 0110 000 0110 1110 1 ep1s80 0000 0010 0000 0000 0111 000 0110 1110 1 notes to ta b l e s 3 ? 2 and 3?3 : (1) the most significant bit (msb) is on the left. (2) the idcode?s least significant bit (lsb) is always 1. 3?4 altera corporation stratix device handbook, volume 1 july 2005 ieee std. 1149.1 (jtag) boundary-scan support figure 3?1 shows the timing requirements for the jtag signals. figure 3?1. stratix jtag waveforms table 3?4 shows the jtag timing parameters and values for stratix devices. table 3?4. stratix jtag ti ming parameters & values symbol parameter min max unit t jcp tck clock period 100 ns t jch tck clock high time 50 ns t jcl tck clock low time 50 ns t jpsu jtag port setup time 20 ns t jph jtag port hold time 45 ns t jpco jtag port clock to output 25 ns t jpzx jtag port high impedance to valid output 25 ns t jpxz jtag port valid output to high impedance 25 ns t jssu capture register setup time 20 ns t jsh capture register hold time 45 ns t jsco update register clock to output 35 ns t jszx update register high impedance to valid output 35 ns t jsxz update register valid output to high impedance 35 ns tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms si g nal to be captured si g nal to be driven t jszx t jssu t jsh t jsco t jsxz altera corporation 3?5 july 2005 stratix device handbook, volume 1 configuration & testing 1 stratix, stratix ii, cyclone ? , and cyclone ii devices must be within the first 17 devices in a jt ag chain. all of these devices have the same jtag controller. if any of the stratix, stratix ii, cyclone, and cyclone ii devices ar e in the 18th or after they will fail configuration. this does not affect signaltap ii. f for more information on jtag, see the following documents: an 39: ieee std. 1149.1 (jtag) bounda ry-scan testing in altera devices jam programming & test language specification signaltap ii embedded logic analyzer stratix devices feature the signalta p ii embedded logic analyzer, which monitors design operation over a peri od of time throug h the ieee std. 1149.1 (jtag) circuitry. you can analyz e internal logic at speed without bringing internal signals to the i/o pins. this feature is particularly important for advanced packag es, such as fineline bga ? packages, because it can be difficult to add a connection to a pin during the debugging process after a board is designed and manufactured. configuration the logic, circuitry, and interconne cts in the stratix architecture are configured with cmos sram elements. altera ? devices are reconfigurable. because every device is tested with a high-coverage production test program, you do not have to perform fault testing and can focus on simulation and design verification. stratix devices are configured at system power-up with data stored in an altera serial configuration device or provided by a system controller. altera offers in-system programmabi lity (isp)-capable configuration devices that configure stratix devices via a serial data stream. stratix devices can be configured in under 100 ms using 8-bit parallel data at 100 mhz. the stratix device?s optimized interface allows microprocessors to configure it serially or in parallel, and synchr onously or asynchronously. the interface also enables microprocessors to treat stratix devices as memory and configure them by writing to a virtual memory location, making reconfiguration easy. after a stratix device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. real-time changes can be made during system operation, enabling innovative reconfigurable computing applications. operating modes the stratix architecture uses sram configuration elements that require configuration data to be loaded each time the circuit powers up. the process of physically loading the sr am data into the device is called configuration. during initialization, which occurs immediately after 3?6 altera corporation stratix device handbook, volume 1 july 2005 configuration configuration, the device resets regist ers, enables i/o pins, and begins to operate as a logic device. the i/o pins are tri-stated during power-up, and before and during configuration. together, the configuration and initialization processes are called command mode. normal device operation is called user mode. sram configuration elements allow stratix devices to be reconfigured in- circuit by loading new configuration data into the device. with real-time reconfiguration, the device is forced into command mode with a device pin. the configuration process loads different configuration data, reinitializes the device, and resumes user-mode operation. you can perform in-field upgrades by distribu ting new configuration files either within the system or remotely. porsel is a dedicated input pin used to select por delay times of 2 ms or 100 ms during power-up. when the porsel pin is connected to ground, the por time is 100 ms; when the porsel pin is connected to v cc , the por time is 2 ms. the nio_pullup pin enables a built-in weak pull-up resistor to pull all user i/o pins to v ccio before and during device configuration. if nio_pullup is connected to v cc during configuration, the weak pull- ups on all user i/o pins are disabled . if connected to ground, the pull-ups are enabled during configuration. the nio_pullup pin can be pulled to 1.5, 1.8, 2.5, or 3.3 v for a logic level high. vccsel is a dedicated input that is used to choose whether all dedicated configuration and jtag input pins ca n accept 1.5 v/1.8 v or 2.5 v/3.3 v during configuration. a logic low sets 3.3 v/2.5 v, and a logic high sets 1.8 v/1.5 v. vccsel affects the following pins: tdi , tms , tck , trst , msel0 , msel1 , msel2 , nconfig , nce , dclk , pll_ena , conf_done , nstatus . the vccsel pin can be pulled to 1.5, 1.8, 2.5, or 3.3 v for a logic level high. the vccsel signal does not control the dual-purpose configuration pins such as the data[7..0] and ppa pins ( nws , nrs , cs , ncs , and rdynbsy ). during configuration, these dual-purpose pins will drive out voltage levels corresponding to the v ccio supply voltage that powers the i/o bank containing the pin. after co nfiguration, the dual-purpose pins use i/o standards specified in the user design. tdo and nceo drive out at the same voltages as the v ccio supply that powers the i/o bank containing th e pin. users must select the v ccio supply for bank containing tdo accordingly. for ex ample, when using the byteblaster ? mv cable, the v ccio for the bank containing tdo must be powered up at 3.3 v. altera corporation 3?7 july 2005 stratix device handbook, volume 1 configuration & testing configuring stratix fpgas with jrunner jrunner is a software driver that configures altera fpgas, including stratix fpgas, through th e byteblaster ii or by teblastermv cables in jtag mode. the programming input file supported is in raw binary file ( .rbf ) format. jrunner also requires a chain description file ( .cdf ) generated by the quartus ii software. jrunner is targeted for embedded jtag configuration. the source code is developed for the windows nt operating system (os), but can be cus tomized to run on other platforms. for more information on the jrunne r software driver, see the jrunner software driver: an embedded so lution to the jtag configuration white paper and the source files on the altera web site ( www.altera.com ). configuration schemes you can load the configuration data for a stratix device with one of five configuration schemes (see table 3?5 ), chosen on the basis of the target application. you can use a configuration device, intelligent controller, or the jtag port to configure a stratix device. a configuration device can automatically configure a strati x device at system power-up. multiple stratix devices can be configured in any of five configuration schemes by connecting th e configuration enable ( nce ) and configuration enable output ( nceo ) pins on each device. partial reconfiguration the enhanced plls within the stratix device family support partial reconfiguration of their multiply, di vide, and time delay settings without reconfiguring the entire device. you ca n use either serial data from the logic array or regular i/o pins to pr ogram the pll?s counter settings in a serial chain. this option provides considerable flexibility for frequency table 3?5. data sources for configuration configuration sc heme data source configuration device enhanced or epc2 configuration device passive serial (ps) masterblaster, byteblastermv, or byteblaster ii download cable or serial data source passive parallel asynchronous (ppa) parallel data source fast passive parallel parallel data source jtag masterblaster, byteblastermv, or byteblaster ii download cable, a microprocessor with a jam or jbc file, or jrunner 3?8 altera corporation stratix device handbook, volume 1 july 2005 configuration synthesis, allowing real-time variat ion of the pll frequency and delay. the rest of the device is functional while reconfiguring the pll. see the stratix architecture chapter of the stratix device handbook, volume 1 for more information on stratix plls. remote update co nfiguration modes stratix devices also support remote configuration using an altera enhanced configuration device (e.g., epc16, epc8, and epc4 devices) with page mode selection. factory configuration data is stored in the default page of the configuration device. this is the default configuration that contains the design required to control remote updates and handle or recover from errors. you write the factory configuration once into the flash memory or configuration device. remote update data can update any of the remaining pages of the config uration device. if there is an error or corruption in a remote update co nfiguration, the configuration device reverts back to the factory configuration information. there are two remote configuration modes: remote and local configuration. you can use the remote update configuration mode for all three configuration modes: serial, pa rallel synchronou s, and parallel asynchronous. configuration devices (for example, epc16 devices) only support serial and parallel synchron ous modes. asynchronous parallel mode allows remote updates when an intelligent host is used to configure the stratix device. this host must suppo rt page mode settings similar to an epc16 device. remote update mode when the stratix device is firs t powered up in remote update programming mode, it loads the configuration located at page address ? 000 .? the factory configuration should always be located at page address ? 000 ,? and should never be remotely updated. the factory configuration contains the requir ed logic to perform the following operations: determine the page address/load lo cation for the next application?s configuration data recover from a previous configuration error receive new configuration data and write it into the configuration device the factory configuration is the defa ult and takes control if an error occurs while loading the application configuration. altera corporation 3?9 july 2005 stratix device handbook, volume 1 configuration & testing while in the factory configuration, the factory-configuration logic performs the following operations: loads a remote update-control register to determine the page address of the new application configuration determines whether to enable a user watchdog timer for the application configuration determines what the watchdog time r setting should be if it is enabled the user watchdog timer is a coun ter that must be continually reset within a specific amount of time in the user mode of an application configuration to ensure that valid co nfiguration occurred during a remote update. only valid application configurations designed for remote update can reset the user watchdog timer in user mode. if a valid application configuration does not re set the user watchdog timer in a specific amount of time, the timer up dates a status register and loads the factory configuration. the user watchd og timer is automatically disabled for factory configurations. if an error occurs in loading th e application configuration, the configuration logic writes a status register to specify the cause of the error. once this occurs, the stratix devi ce automatically loads the factory configuration, which read s the status register and determines the reason for reconfiguration. based on the re ason, the factory co nfiguration will take appropriate steps and will write the remote update control register to specify the next application configuration page to be loaded. when the stratix device successfully loads the application configuration, it enters into user mode. the strati x device then executes the main application of the user. intellectua l property (ip), such as a nios ? (16-bit isa) and nios ? ii (32-bit isa) embedded processors, can help the stratix device determine when remote upda te is coming. the nios embedded processor or user logic receives incoming data, writes it to the configuration device, and loads the factory configuration. the factory configuration will read the remote update status register and determine the valid application configuration to load. figure 3?2 shows the stratix remote update. figure 3?3 shows the transition diagram for remote update mode. 3?10 altera corporation stratix device handbook, volume 1 july 2005 configuration figure 3?2. stratix devi ce remote update note to figure 3?2 : (1) when the stratix device is configured with the factory co nfiguration, it can handle upda te data from epc16, epc8, or epc4 configuration device pages and point to the next page in the configuration device. watchdo g timer stratix device new remote confi g uration data confi g uration device application confi g uration application confi g uration factory confi g uration (1) c on f i g u rat ion de vi ce updates strat ix de vi ce wi t h f act o r y c on f i g u rat ion ( t o h a n d l e update ) o r n e w a pp li cat ion c on f i g u rat ion page 7 page 6 page 0 altera corporation 3?11 july 2005 stratix device handbook, volume 1 configuration & testing figure 3?3. remote update transition diagram notes (1) , (2) notes to figure 3?3 : (1) remote update of application config uration is controlled by a nios embedded processor or user logic programmed in the factory or application configurations. (2) up to seven pages can be specified allowing up to seven different configuration applications. confi g uration error confi g uration error application 1 confi g uration confi g uration error factory confi g uration reload an application reload an application application n confi g uration power-up 3?12 altera corporation stratix device handbook, volume 1 july 2005 stratix automated single event upset (seu) detection local update mode local update mode is a simplified version of the remote update. this feature is intended for simple systems that need to load a single application configuration immediately upon power up without loading the factory configuration first. local update designs have only one application configuratio n to load, so it does not require a factory configuration to determine which application configuration to use. figure 3?4 shows the transition diagram for local update mode. figure 3?4. local update transition diagram stratix automated single event upset (seu) detection stratix devices offer on-chip circuitr y for automated checking of single event upset (seu) detection. fpga devi ces that operate at high elevations or in close proximity to earth?s north or south pole require periodic checks to ensure continued data integrity. the error detection cyclic redundancy check (crc) feature controlled by the device & pin options dialog box in the quartus ii software uses a 32-bit crc circuit to ensure data reliability and is one of the best options for mitigating seu. nconfig nconfig confi g uration error application confi g uration confi g uration error factory confi g uration power-up or nconfig altera corporation 3?13 july 2005 stratix device handbook, volume 1 configuration & testing for stratix, the crc is computed by the quartus ii software and downloaded into the device as a part of the configuration bit stream. the crc_error pin reports a soft error when configuration sram data is corrupted, triggering device reconfiguration. custom-built circuitry dedicated circuitry is built in th e stratix devices to perform error detection automatically. you can use th e built-in dedicated circuitry for error detection using crc feature in stratix devices, eliminating the need for external logic. this circui try will perform error detection automatically when enabled. this error detection circuitry in stratix devices constantly checks for errors in the configuration sram cells while the device is in user mode. yo u can monitor one external pin for the error and use it to trigger a re-configu ration cycle. select the desired time between checks by adjusting a built-in clock divider. software interface in the quartus ii software version 4.1 and later, you can turn on the automated error detection crc feature in the device & pin options dialog box. this dialog box allows you to enable the feature and set the internal frequency of the crc between 400 khz to 100 mhz. this controls the rate that the crc circuitry verifi es the internal configuration sram bits in the fpga device. for more information on crc, see an 357: error detection using crc in altera fpga devices . temperature sensing diode stratix devices include a diode-connected transistor for use as a temperature sensor in power manageme nt. this diode is used with an external digital thermometer devi ce such as a max1617a or max1619 from maxim integrated products. these devices steer bias current through the stratix diode, measuring forward voltage and converting this reading to temperature in the form of an 8-bit signed number (7 bits plus sign). the external device?s output re presents the junction temperature of the stratix device and can be used for intelligent power management. the diode requires two pins ( tempdiodep and tempdioden ) on the stratix device to connect to the exte rnal temperature-sensing device, as shown in figure 3?5 . the temperature sensing diode is a passive element and therefore can be used before the stratix device is powered. 3?14 altera corporation stratix device handbook, volume 1 july 2005 temperature sensing diode figure 3?5. external temperature-sensing diode table 3?6 shows the specifications for bias voltage and current of the stratix temperature sensing diode. table 3?6. temperature-sensing di ode electrical characteristics parameter minimum typical maximum unit i bias high 80 100 120 a i bias low 8 10 12 a v bp ? v bn 0.3 0.9 v v bn 0.7 v series resistance 3 w stratix device temperature-sensin g device tempdiodep tempdioden altera corporation 3?15 july 2005 stratix device handbook, volume 1 configuration & testing the temperature-sensing diode works for the entire operating range shown in figure 3?6 . figure 3?6. temperature vs. temperature-sensing diode voltage 0.90 0.85 0.95 0.75 0.65 voltage (across diode) temperature ( c) 0.55 0.45 0.60 0.50 0.40 0.70 0.80 ? 55 ? 30 ? 520457095120 10 a bias current 100 a bias current 3?16 altera corporation stratix device handbook, volume 1 july 2005 temperature sensing diode altera corporation 4?1 july 2005 4. dc & switching characteristics operating conditions stratix ? devices are offered in both co mmercial and indu strial grades. industrial devices are offered in -6 and -7 speed grades and commercial devices are offered in -5 (fastest), -6 , -7, and -8 speed grades. this section specifies the operation conditions fo r operating junction temperature, v ccint and v ccio voltage levels, and input voltage requirements. the voltage specifications in this section are specified at the pins of the device (and not the power supply). if the de vice operates outside these ranges, then all dc and ac specifications are not guaranteed. furthermore, the reliability of the device may be affected. the timing parameters in this chapter apply to both commercial an d industrial temperature ranges unless otherwise stated. tables 4?1 through 4?8 provide information on absolute maximum ratings. table 4?1. stratix device absolute maximum ratings notes (1) , (2) symbol parameter conditions minimum maximum unit v ccint supply voltage with respect to ground ?0.5 2.4 v v ccio ?0.5 4.6 v v i dc input voltage (3) ?0.5 4.6 v i out dc output current, per pin ?25 40 ma t stg storage temperature no bias ?65 150 c t j junction temperature bga packages under bias 135 c table 4?2. stratix device recommend ed operating conditions (part 1 of 2) symbol parameter conditions minimum maximum unit v ccint supply voltage for internal logic and input buffers (4) 1.425 1.575 v s51004-3.3 4?2 altera corporation stratix device handbook, volume 1 july 2005 operating conditions v ccio supply voltage for output buffers, 3.3-v operation (4) , (5) 3.00 (3.135) 3.60 (3.465) v supply voltage for output buffers, 2.5-v operation (4) 2.375 2.625 v supply voltage for output buffers, 1.8-v operation (4) 1.71 1.89 v supply voltage for output buffers, 1.5-v operation (4) 1.4 1.6 v v i input voltage (3) , (6) ?0.5 4.0 v v o output voltage 0 v ccio v t j operating junction temperature for commercial use 0 85 c for industrial use ?40 100 c table 4?3. stratix device dc operating conditions note (7) (part 1 of 2) symbol parameter conditions minimum typical maximum unit i i input pin leakage current v i = v cciomax to 0 v (8) ?10 10 a i oz tri-stated i/o pin leakage current v o = v cciomax to 0 v (8) ?10 10 a i cc0 v cc supply current (standby) (all memory blocks in power-down mode) v i = ground, no load, no toggling inputs ma ep1s10. v i = ground, no load, no toggling inputs 37 ma ep1s20. v i = ground, no load, no toggling inputs 65 ma ep1s25. v i = ground, no load, no toggling inputs 90 ma ep1s30. v i = ground, no load, no toggling inputs 114 ma ep1s40. v i = ground, no load, no toggling inputs 145 ma ep1s60. v i = ground, no load, no toggling inputs 200 ma ep1s80. v i = ground, no load, no toggling inputs 277 ma table 4?2. stratix device recommend ed operating conditions (part 2 of 2) symbol parameter conditions minimum maximum unit altera corporation 4?3 july 2005 stratix device handbook, volume 1 dc & switching characteristics r conf value of i/o pin pull- up resistor before and during configuration v ccio = 3.0 v (9) 20 50 k v ccio = 2.375 v (9) 30 80 k v ccio = 1.71 v (9) 60 150 k table 4?4. lvttl specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 3.0 3.6 v v ih high-level input voltage 1.7 4.1 v v il low-level input voltage ?0.5 0.7 v v oh high-level output voltage i oh = ?4 to ?24 ma (10) 2.4 v v ol low-level output voltage i ol = 4 to 24 ma (10) 0.45 v table 4?5. lvcmos specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 3.0 3.6 v v ih high-level input voltage 1.7 4.1 v v il low-level input voltage ?0.5 0.7 v v oh high-level output voltage v ccio = 3.0, i oh = ?0.1 ma v ccio ? 0.2 v v ol low-level output voltage v ccio = 3.0, i ol = 0.1 ma 0.2 v table 4?6. 2.5-v i/o specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 2.375 2.625 v v ih high-level input voltage 1.7 4.1 v v il low-level input voltage ?0.5 0.7 v v oh high-level output voltage i oh = ?1 ma (10) 2.0 v v ol low-level output voltage i ol = 1 ma (10) 0.4 v table 4?3. stratix device dc operating conditions note (7) (part 2 of 2) symbol parameter conditions minimum typical maximum unit 4?4 altera corporation stratix device handbook, volume 1 july 2005 operating conditions table 4?7. 1.8-v i/o specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 1.65 1.95 v v ih high-level input voltage 0.65 v ccio 2.25 v v il low-level input voltage ?0.3 0.35 v ccio v v oh high-level output voltage i oh = ?2 to ?8 ma (10) v ccio ? 0.45 v v ol low-level output voltage i ol = 2 to 8 ma (10) 0.45 v table 4?8. 1.5-v i/o specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 1.4 1.6 v v ih high-level input voltage 0.65 v ccio v ccio + 0.3 v v il low-level input voltage ?0.3 0.35 v ccio v v oh high-level output voltage i oh = ?2 ma (10) 0.75 v ccio v v ol low-level output voltage i ol = 2 ma (10) 0.25 v ccio v notes to ta b l e s 4 ? 1 through 4?8 : (1) see the operating requirements for altera devices data sheet . (2) conditions beyond those listed in table 4?1 may cause permanent damage to a device. additionally, device operation at the absolute maximum ratings for extended pe riods of time may have adve rse affects on the device. (3) minimum dc input is ?0.5 v. during transitions, the in puts may undershoot to ?2.0 v for input currents less than 100 ma and periods shorter than 20 ns, or overshoot to the voltage shown in table 4?9 , based on input duty cycle for input currents less than 100 ma. the overshoot is depe ndent upon duty cycle of th e signal. the dc case is equivalent to 100% duty cycle. (4) maximum v cc rise time is 100 ms, and v cc must rise monotonically. (5) v ccio maximum and minimum conditions for lvpecl, lvds, and 3.3-v pcml are shown in parentheses. (6) all pins, including dedicated inputs, clock, i/o, and jtag pins, may be driven before v ccint and v ccio are powered. (7) typical values are for t a = 25c, v ccint = 1.5 v, and v ccio = 1.5 v, 1.8 v, 2.5 v, and 3.3 v. (8) this value is specified for normal device operation. the value may vary during power-up. this applies for all v ccio settings (3.3, 2.5, 1.8, and 1.5 v). (9) pin pull-up resistance values will lower if an external source drives the pin higher than v ccio . (10) drive strength is programmable according to the values shown in the stratix architecture chapter of the stratix device handbook, volume 1 . table 4?9. overshoot input voltage with respect to duty cycle (part 1 of 2) vin (v) maximum duty cycle (%) 4.0 100 4.1 90 4.2 50 altera corporation 4?5 july 2005 stratix device handbook, volume 1 dc & switching characteristics figures 4?1 and 4?2 show receiver input and transmitter output waveforms, respectively, for all diffe rential i/o standards (lvds, 3.3-v pcml, lvpecl, and hypert ransport technology). figure 4?1. receiver input waveform s for differential i/o standards 4.3 30 4.4 17 4.5 10 table 4?9. overshoot input voltage with respect to duty cycle (part 2 of 2) vin (v) maximum duty cycle (%) single-ended waveform differential waveform positive channel (p) = v ih ne g ative channel (n) = v il ground v id v id v id v cm p ? n = 0 v 4?6 altera corporation stratix device handbook, volume 1 july 2005 operating conditions figure 4?2. transmitter output wavefo rms for differential i/o standards tables 4?10 through 4?33 recommend operating conditions, dc operating conditions, and ca pacitance for 1.5-v stratix devices. single-ended waveform differential waveform positive channel (p) = v oh ne g ative channel (n) = v ol ground v od v od v od p ? n = 0 v v cm table 4?10. 3.3-v lvds i/o specifications (part 1 of 2) symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 3.135 3.3 3.465 v v id (6) input differential voltage swing (single-ended) 0.1 v v cm < 1.1 v w = 1 through 10 300 1,000 mv 1.1 v v cm 1.6 v w = 1 200 1,000 mv 1.1 v v cm 1.6 v w = 2 through10 100 1,000 mv 1.6 v < v cm 1.8 v w = 1 through 10 300 1,000 mv altera corporation 4?7 july 2005 stratix device handbook, volume 1 dc & switching characteristics v icm input common mode voltage (6) lv d s 0.3 v v id 1.0 v w = 1 through 10 100 1,100 mv lv d s 0.3 v v id 1.0 v w = 1 through 10 1,600 1,800 mv lv d s 0.2 v v id 1.0 v w = 1 1,100 1,600 mv lv d s 0.1 v v id 1.0 v w = 2 through 10 1,100 1,600 mv v od (1) output differential voltage (single-ended) r l = 100 250 375 550 mv v od change in v od between high and low r l = 100 50 mv v ocm output common mode voltage r l = 100 1,125 1,200 1,375 mv v ocm change in v ocm between high and low r l = 100 50 mv r l receiver differential input discrete resistor (external to stratix devices) 90 100 110 table 4?10. 3.3-v lvds i/o specifications (part 2 of 2) symbol parameter conditions minimum typical maximum unit 4?8 altera corporation stratix device handbook, volume 1 july 2005 operating conditions table 4?11. 3.3-v pcml specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 3.135 3.3 3.465 v v id (peak- to-peak) input differential voltage swing (single-ended) 300 600 mv v icm input common mode voltage 1.5 3.465 v v od output differential voltage (single-ended) 300 370 500 mv v od change in v od between high and low 50 mv v ocm output common mode voltage 2.5 2.85 3.3 v v ocm change in v ocm between high and low 50 mv v t output termination voltage v ccio v r 1 output external pull-up resistors 45 50 55 r 2 output external pull-up resistors 45 50 55 table 4?12. lvpecl specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 3.135 3.3 3.465 v v id (peak- to-peak) input differential voltage swing (single-ended) 300 1,000 mv v icm input common mode voltage 12v v od output differential voltage (single-ended) r l = 100 525 700 970 mv v ocm output common mode voltage r l = 100 1.5 1.7 1.9 v r l receiver differential input resistor 90 100 110 altera corporation 4?9 july 2005 stratix device handbook, volume 1 dc & switching characteristics table 4?13. hypertransport te chnology spec ifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 2.375 2.5 2.625 v v id (peak- to-peak) input differential voltage swing (single-ended) 300 900 mv v icm input common mode voltage 300 900 mv v od output differential voltage (single-ended) r l = 100 380 485 820 mv v od change in v od between high and low r l = 100 50 mv v ocm output common mode voltage r l = 100 440 650 780 mv v ocm change in v ocm between high and low r l = 100 50 mv r l receiver differential input resistor 90 100 110 table 4?14. 3.3-v pci specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.3 3.6 v v ih high-level input voltage 0.5 v ccio v ccio + 0.5 v v il low-level input voltage ?0.5 0.3 v ccio v v oh high-level output voltage i out = ?500 a0.9 v ccio v v ol low-level output voltage i out = 1,500 a0.1 v ccio v 4?10 altera corporation stratix device handbook, volume 1 july 2005 operating conditions table 4?15. pci-x 1.0 specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.6 v v ih high-level input voltage 0.5 v ccio v ccio + 0.5 v v il low-level input voltage ?0.5 0.35 v ccio v v ipu input pull-up voltage 0.7 v ccio v v oh high-level output voltage i out = ?500 a0.9 v ccio v v ol low-level output voltage i out = 1,500 a0.1 v ccio v table 4?16. gtl+ i/o specifications symbol parameter conditions minimum typical maximum unit v tt termination voltage 1.35 1.5 1.65 v v ref reference voltage 0.88 1.0 1.12 v v ih high-level input voltage v ref + 0.1 v v il low-level input voltage v ref ? 0.1 v v ol low-level output voltage i ol = 34 ma (3) 0.65 v table 4?17. gtl i/o specifications symbol parameter conditions minimum typical maximum unit v tt termination voltage 1.14 1.2 1.26 v v ref reference voltage 0.74 0.8 0.86 v v ih high-level input voltage v ref + 0.05 v v il low-level input voltage v ref ? 0.05 v v ol low-level output voltage i ol = 40 ma (3) 0.4 v altera corporation 4?11 july 2005 stratix device handbook, volume 1 dc & switching characteristics table 4?18. sstl-18 clas s i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.65 1.8 1.95 v v ref reference voltage 0.8 0.9 1.0 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ih(dc) high-level dc input voltage v ref + 0.125 v v il(dc) low-level dc input voltage v ref ? 0.125 v v ih(ac) high-level ac input voltage v ref + 0.275 v v il(ac) low-level ac input voltage v ref ? 0.275 v v oh high-level output voltage i oh = ?6.7 ma (3) v tt + 0.475 v v ol low-level output voltage i ol = 6.7 ma (3) v tt ? 0.475 v table 4?19. sstl-18 clas s ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.65 1.8 1.95 v v ref reference voltage 0.8 0.9 1.0 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ih(dc) high-level dc input voltage v ref + 0.125 v v il(dc) low-level dc input voltage v ref ? 0.125 v v ih(ac) high-level ac input voltage v ref + 0.275 v v il(ac) low-level ac input voltage v ref ? 0.275 v v oh high-level output voltage i oh = ?13.4 ma (3) v tt + 0.630 v v ol low-level output voltage i ol = 13.4 ma (3) v tt ? 0.630 v 4?12 altera corporation stratix device handbook, volume 1 july 2005 operating conditions table 4?20. sstl-2 class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.375 2.5 2.625 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ref reference voltage 1.15 1.25 1.35 v v ih(dc) high-level dc input voltage v ref + 0.18 3.0 v v il(dc) low-level dc input voltage ?0.3 v ref ? 0.18 v v ih(ac) high-level ac input voltage v ref + 0.35 v v il(ac) low-level ac input voltage v ref ? 0.35 v v oh high-level output voltage i oh = ?8.1 ma (3) v tt + 0.57 v v ol low-level output voltage i ol = 8.1 ma (3) v tt ? 0.57 v table 4?21. sstl-2 class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.375 2.5 2.625 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ref reference voltage 1.15 1.25 1.35 v v ih(dc) high-level dc input voltage v ref + 0.18 v ccio + 0.3 v v il(dc) low-level dc input voltage ?0.3 v ref ? 0.18 v v ih(ac) high-level ac input voltage v ref + 0.35 v v il(ac) low-level ac input voltage v ref ? 0.35 v v oh high-level output voltage i oh = ?16.4 ma (3) v tt + 0.76 v v ol low-level output voltage i ol = 16.4 ma (3) v tt ? 0.76 v table 4?22. sstl-3 class i specifications (part 1 of 2) symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.3 3.6 v v tt termination voltage v ref ? 0.05 v ref v ref + 0.05 v v ref reference voltage 1.3 1.5 1.7 v v ih(dc) high-level dc input voltage v ref + 0.2 v ccio + 0.3 v v il(dc) low-level dc input voltage ?0.3 v ref ? 0.2 v v ih(ac) high-level ac input voltage v ref + 0.4 v altera corporation 4?13 july 2005 stratix device handbook, volume 1 dc & switching characteristics v il(ac) low-level ac input voltage v ref ? 0.4 v v oh high-level output voltage i oh = ?8 ma (3) v tt + 0.6 v v ol low-level output voltage i ol = 8 ma (3) v tt ? 0.6 v table 4?23. sstl-3 class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.3 3.6 v v tt termination voltage v ref ? 0.05 v ref v ref + 0.05 v v ref reference voltage 1.3 1.5 1.7 v v ih(dc) high-level dc input voltage v ref + 0.2 v ccio + 0.3 v v il(dc) low-level dc input voltage ?0.3 v ref ? 0.2 v v ih(ac) high-level ac input voltage v ref + 0.4 v v il(ac) low-level ac input voltage v ref ? 0.4 v v oh high-level output voltage i oh = ?16 ma (3) v tt + 0.8 v v ol low-level output voltage i ol = 16 ma (3) v tt ? 0.8 v table 4?24. 3.3-v agp 2 specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.15 3.3 3.45 v v ref reference voltage 0.39 v ccio 0.41 v ccio v v ih high-level input voltage (4) 0.5 v ccio v ccio + 0.5 v v il low-level input voltage (4) 0.3 v ccio v v oh high-level output voltage i out = ?0.5 ma 0.9 v ccio 3.6 v v ol low-level output voltage i out = 1.5 ma 0.1 v ccio v table 4?25. 3.3-v agp 1 specifications (part 1 of 2) symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.15 3.3 3.45 v v ih high-level input voltage (4) 0.5 v ccio v ccio + 0.5 v v il low-level input voltage (4) 0.3 v ccio v table 4?22. sstl-3 class i specifications (part 2 of 2) symbol parameter conditions minimum typical maximum unit 4?14 altera corporation stratix device handbook, volume 1 july 2005 operating conditions v oh high-level output voltage i out = ?0.5 ma 0.9 v ccio 3.6 v v ol low-level output voltage i out = 1.5 ma 0.1 v ccio v table 4?26. 1.5-v hstl class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.4 1.5 1.6 v v ref input reference voltage 0.68 0.75 0.9 v v tt termination voltage 0.7 0.75 0.8 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = ?8 ma (3) v ccio ? 0.4 v v ol low-level output voltage i ol = 8 ma (3) 0.4 v table 4?27. 1.5-v hstl class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.4 1.5 1.6 v v ref input reference voltage 0.68 0.75 0.9 v v tt termination voltage 0.7 0.75 0.8 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = ?16 ma (3) v ccio ? 0.4 v v ol low-level output voltage i ol = 16 ma (3) 0.4 v table 4?25. 3.3-v agp 1 specifications (part 2 of 2) symbol parameter conditions minimum typical maximum unit altera corporation 4?15 july 2005 stratix device handbook, volume 1 dc & switching characteristics table 4?28. 1.8-v hstl class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.65 1.80 1.95 v v ref input reference voltage 0.70 0.90 0.95 v v tt termination voltage v ccio 0.5 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.5 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = ?8 ma (3) v ccio ? 0.4 v v ol low-level output voltage i ol = 8 ma (3) 0.4 v table 4?29. 1.8-v hstl class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.65 1.80 1.95 v v ref input reference voltage 0.70 0.90 0.95 v v tt termination voltage v ccio 0.5 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.5 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = ?16 ma (3) v ccio ? 0.4 v v ol low-level output voltage i ol = 16 ma (3) 0.4 v table 4?30. 1.5-v differential hstl cl ass i & class ii specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 1.4 1.5 1.6 v v dif (dc) dc input differential voltage 0.2 v v cm (dc) dc common mode input voltage 0.68 0.9 v v dif (ac) ac differential input voltage 0.4 v 4?16 altera corporation stratix device handbook, volume 1 july 2005 operating conditions table 4?31. ctt i/o specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.05 3.3 3.6 v v tt /v ref termination and input reference voltage 1.35 1.5 1.65 v v ih high-level input voltage v ref + 0.2 v v il low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = ?8 ma v ref + 0.4 v v ol low-level output voltage i ol = 8 ma v ref ? 0.4 v i o output leakage current (when output is high z ) gnd v out v ccio ?10 10 a table 4?32. bus hold parameters parameter conditions v ccio level unit 1.5 v1.8 v2.5 v3.3 v min max min max min max min max low sustaining current v in > v il (maximum) 25 30 50 70 a high sustaining current v in < v ih (minimum) -25 ?30 ?50 ?70 a low overdrive current 0 v < v in < v ccio 160 200 300 500 a high overdrive current 0 v < v in < v ccio -160 ?200 ?300 ?500 a bus-hold trip point 0.5 1.0 0.68 1.07 0.7 1.7 0.8 2.0 v altera corporation 4?17 july 2005 stratix device handbook, volume 1 dc & switching characteristics power consumption altera ? offers two ways to calculate power for a design: the altera web power calculator and the powergauge tm feature in the quartus ? ii software. the interactive power calculator on th e altera web site is typically used prior to designing the fpga in order to get a magnitude estimate of the device power. the quartus ii software powergauge feature allows you to apply test vectors against your design for more accurate power consumption modeling. in both cases, these calculations should only be used as an estimation of power, not as a specification. stratix devices require a certain amount of power-up current to successfully power up because of th e small process ge ometry on which they are fabricated. table 4?34 shows the maximum power-up current (i ccint ) required to power a stratix device. this specification is for commercial operating conditions. measurements were perf ormed with an isolated stratix device on the board to characterize the power-up current of an isolated table 4?33. stratix device capacitance note (5) symbol parameter minimum typical maximum unit c iotb input capacitance on i/o pins in i/o banks 3, 4, 7, and 8. 11.5 pf c iolr input capacitance on i/o pins in i/o banks 1, 2, 5, and 6, including high-speed differential receiver and transmitter pins. 8.2 pf c clktb input capacitance on top/bottom clock input pins: clk[4:7] and clk[12:15] . 11.5 pf c clklr input capacitance on left/right clock inputs: clk1 , clk3 , clk8 , clk10 . 7.8 pf c clklr+ input capacitance on left/right clock inputs: clk0 , clk2 , clk9 , and clk11 . 4.4 pf notes to tables 4?10 through 4?33 : (1) when tx_outclock port of altlvds_tx megafunction is 717 mhz, v od(min) = 235 mv on the output clock pin. (2) pin pull-up resistance values will lower if an external source drives the pin higher than v ccio . (3) drive strength is programmable ac cording to the values shown in the stratix architecture chapter of the stratix device handbook, volume 1 . (4) v ref specifies the center point of the switching range. (5) capacitance is sample-tested only. capacitance is me asured using time-domain reflections (tdr). measurement accuracy is within 0.5 pf. (6) v io and v cm have multiple ranges and values for j=1 through 10. 4?18 altera corporation stratix device handbook, volume 1 july 2005 power consumption device. decoupling capacitors were not used in this measurement. to factor in the current for decoupling capacitors, sum up the current for each capacitor using the following equation: i = c (dv/dt) if the regulator or power supply mini mum output current is more than the stratix device requires, then the device may consume more current than the maximum current listed in table 4?34 . however, the device does not require any more current to successf ully power up than what is listed in table 4?34 . the exact amount of current consumed varies according to the process, temperature, and power ramp rate. st ratix devices typically require less current during power up than shown in table 4?34 . the user-mode current during device operation is generally higher than the power-up current. the duration of the i ccint power-up requirement depends on the v ccint voltage supply rise time. the power-up current consumption drops when the v ccint supply reaches approximately 0.75 v. table 4?34. stratix power-up current (i ccint ) requirements note (1) device power-up current requirement unit typical maximum ep1s10 250 700 ma ep1s20 400 1,200 ma ep1s25 500 1,500 ma ep1s30 550 1,900 ma ep1s40 650 2,300 ma ep1s60 800 2,600 ma ep1s80 1,000 3,000 ma note to table 4?34 : (1) the maximum test conditions are for 0 c and typical test conditions are for 40 c. altera corporation 4?19 july 2005 stratix device handbook, volume 1 dc & switching characteristics timing model the directdrive ? technology and multitrack ? interconnect ensure predictable performance, accurate simulation, and ac curate timing analysis across all stratix device densities and speed grades. this section describes and specifies the performance, internal, external, and pll timing specifications. all specifications are representative of worst-case supply voltage and junction temperature conditions. preliminary & final timing timing models can have either preliminary or final status. the quartus ii software issues an informational me ssage during the design compilation if the timing models are preliminary. table 4?35 shows the status of the stratix device timing models. preliminary status means the timing model is subject to change. initially, timing numbers are created using simulation results, process data, and other known parameters. these tests are used to make the preliminary numbers as close to the actual timing parameters as possible. final timing numbers are based on ac tual device operation and testing. these numbers reflect the actual perf ormance of the device under worst- case voltage and junction temperature conditions. table 4?35. stratix device timing model status device preliminary final ep1s10 v ep1s20 v ep1s25 v ep1s30 v ep1s40 v ep1s60 v ep1s80 v 4?20 altera corporation stratix device handbook, volume 1 july 2005 timing model performance table 4?36 shows stratix performance fo r some common designs. all performance values were obtained with quartus ii software compilation of lpm, or megacore ? functions for the fir and fft designs. table 4?36. stratix performance (part 1 of 2) notes (1) , (2) applications resources used performance les trimatrix memory blocks dsp blocks -5 speed grade -6 speed grade -7 speed grade -8 speed grade units le 16-to-1 multiplexer (1) 22 0 0 407.83 324.56 288.68 228.67 mhz 32-to-1 multiplexer (3) 46 0 0 318.26 255.29 242.89 185.18 mhz 16-bit counter 16 0 0 422.11 422.11 390.01 348.67 mhz 64-bit counter 64 0 0 321.85 290.52 261.23 220.5 mhz tr i m a t r i x memory m512 block simple dual-port ram 32 18 bit 0 1 0 317.76 277.62 241.48 205.21 mhz fifo 32 18 bit 30 1 0 319.18 278.86 242.54 206.14 mhz tr i m a t r i x memory m4k block simple dual-port ram 128 36 bit 0 1 0 290.86 255.55 222.27 188.89 mhz true dual-port ram 128 18 bit 0 1 0 290.86 255.55 222.27 188.89 mhz fifo 128 36 bit 34 1 0 290.86 255.55 222.27 188.89 mhz tr i m a t r i x memory m-ram block single port ram 4k 144 bit 1 1 0 255.95 223.06 194.06 164.93 mhz simple dual-port ram 4k 144 bit 0 1 0 255.95 233.06 194.06 164.93 mhz true dual-port ram 4k 144 bit 0 1 0 255.95 233.06 194.06 164.93 mhz single port ram 8k 72 bit 0 1 0 278.94 243.19 211.59 179.82 mhz simple dual-port ram 8k 72 bit 0 1 0 255.95 223.06 194.06 164.93 mhz true dual-port ram 8k 72 bit 0 1 0 255.95 223.06 194.06 164.93 mhz single port ram 16k 36 bit 0 1 0 280.66 254.32 221.28 188.00 mhz simple dual-port ram 16k 36 bit 0 1 0 269.83 237.69 206.82 175.74 mhz altera corporation 4?21 july 2005 stratix device handbook, volume 1 dc & switching characteristics tr i m a t r i x memory m-ram block true dual-port ram 16k 36 bit 0 1 0 269.83 237.69 206.82 175.74 mhz single port ram 32k 18 bit 0 1 0 275.86 244.55 212.76 180.83 mhz simple dual-port ram 32k 18 bit 0 1 0 275.86 244.55 212.76 180.83 mhz true dual-port ram 32k 18 bit 0 1 0 275.86 244.55 212.76 180.83 mhz single port ram 64k 9 bit 0 1 0 287.85 253.29 220.36 187.26 mhz simple dual-port ram 64k 9 bit 0 1 0 287.85 253.29 220.36 187.26 mhz true dual-port ram 64k 9 bit 0 1 0 287.85 253.29 220.36 187.26 mhz dsp block 9 9-bit multiplier (3) 0 0 1 335.0 293.94 255.68 217.24 mhz 18 18-bit multiplier (4) 0 0 1 278.78 237.41 206.52 175.50 mhz 36 36-bit multiplier (4) 0 0 1 148.25 134.71 117.16 99.59 mhz 36 36-bit multiplier (5) 0 0 1 278.78 237.41 206.52 175.5 mhz 18-bit, 4-tap fir filter 0 0 1 278.78 237.41 206.52 175.50 mhz larger designs 8-bit, 16-tap parallel fir filter 58 0 4 141.26 133.49 114.88 100.28 mhz 8-bit, 1,024-point fft function 870 5 1 261.09 235.51 205.21 175.22 mhz notes to table 4?36 : (1) these design performance numbers were obtained using the quartus ii software. (2) numbers not listed will be included in a future version of the data sheet. (3) this application uses regi stered inputs and outputs. (4) this application uses registered multiplier input and output stages within the dsp block. (5) this application uses registered multiplier input, pipeline, and output stages within the dsp block. table 4?36. stratix performance (part 2 of 2) notes (1) , (2) applications resources used performance les trimatrix memory blocks dsp blocks -5 speed grade -6 speed grade -7 speed grade -8 speed grade units 4?22 altera corporation stratix device handbook, volume 1 july 2005 timing model internal timing parameters internal timing parame ters are specified on a speed grade basis independent of device density. tables 4?37 through 4?42 describe the stratix device internal timing microparameters for les, ioes, trimatrix ? memory structures, dsp blocks, and multitrack interconnects. table 4?37. le internal timing microparameter descriptions symbol parameter t su le register setup time before clock t h le register hold time after clock t co le register clock-to-output delay t lut le combinatorial lut delay for data-in to data-out t clr minimum clear pulse width t pre minimum preset pulse width t clkhl register minimum clock high or low time. the maximum core clock frequency can be calculated by 1/(2 t clkhl ). table 4?38. ioe internal timing microparameter descriptions symbol parameter t su_r row ioe input register setup time t su_c column ioe input register setup time t h ioe input and output register hold time after clock t co_r row ioe input and output register clock-to-output delay t co_c column ioe input and output register clock-to-output delay t pin2combout_r row input pin to ioe combinatorial output t pin2combout_c column input pin to ioe combinatorial output t combin2pin_r row ioe data input to combinatorial output pin t combin2pin_c column ioe data input to combinatorial output pin t clr minimum clear pulse width t pre minimum preset pulse width t clkhl register minimum clock high or low time. the maximum i/o clock frequency can be calculated by 1/(2 t clkhl ). performance may also be affected by i/o timing, use of pll, and i/o programmable settings. altera corporation 4?23 july 2005 stratix device handbook, volume 1 dc & switching characteristics table 4?39. dsp block internal timing microparameter descriptions symbol parameter t su input, pipeline, and output regist er setup time before clock t h input, pipeline, and output regi ster hold time after clock t co input, pipeline, and output regi ster clock-to-output delay t inreg2pipe9 input register to dsp bloc k pipeline register in 9 9-bit mode t inreg2pipe18 input register to dsp bloc k pipeline register in 18 18-bit mode t pipe2outreg2add dsp block pipeline register to output register delay in two- multipliers adder mode t pipe2outreg4add dsp block pipeline register to output register delay in four- multipliers adder mode t pd9 combinatorial input to output delay for 9 9 t pd18 combinatorial input to output delay for 18 18 t pd36 combinatorial input to output delay for 36 36 t clr minimum clear pulse width t clkhl register minimum clock high or low time. this is a limit on the min time for the clock on the registers in these blocks. the actual performance is dependent upon the internal point-to-point delays in the blocks and may give slower performance as shown in table 4?36 on page 4?20 and as reported by the timing analyzer in the quartus ii software. 4?24 altera corporation stratix device handbook, volume 1 july 2005 timing model table 4?40. m512 block internal t iming microparameter descriptions symbol parameter t m512rc synchronous read cycle time t m512wc synchronous write cycle time t m512weresu write or read enable setup time before clock t m512wereh write or read enable hold time after clock t m512clkensu clock enable setup time before clock t m512clkenh clock enable hold time after clock t m512datasu data setup time before clock t m512datah data hold time after clock t m512waddrsu write address setup time before clock t m512waddrh write address hold time after clock t m512raddrsu read address setup time before clock t m512raddrh read address hold time after clock t m512dataco1 clock-to-output delay when using output registers t m512dataco2 clock-to-output delay without output registers t m512clkhl register minimum clock high or low time. this is a limit on the min time for the clock on the registers in these blocks. the actual performance is dependent upon the internal point-to-point delays in the blocks and may give slower performance as shown in table 4?36 on page 4?20 and as reported by the timing analyzer in the quartus ii software. t m512clr minimum clear pulse width table 4?41. m4k block internal timing microparameter descriptions (part 1 of 2) symbol parameter t m4krc synchronous read cycle time t m4kwc synchronous write cycle time t m4kweresu write or read enable setup time before clock t m4kwereh write or read enable hold time after clock t m4kclkensu clock enable setup time before clock t m4kclkenh clock enable hold time after clock t m4kbesu byte enable setup time before clock t m4kbeh byte enable hold time after clock t m4kdataasu a port data setup time before clock altera corporation 4?25 july 2005 stratix device handbook, volume 1 dc & switching characteristics t m4kdataah a port data hold time after clock t m4kaddrasu a port address setup time before clock t m4kaddrah a port address hold time after clock t m4kdatabsu b port data setup time before clock t m4kdatabh b port data hold time after clock t m4kaddrbsu b port address setup time before clock t m4kaddrbh b port address hold time after clock t m4kdataco1 clock-to-output delay when using output registers t m4kdataco2 clock-to-output delay without output registers t m4kclkhl register minimum clock high or low time. this is a limit on the min time for the clock on the registers in these blocks. the actual performance is dependent upon the internal point-to-point delays in the blocks and may give slower performance as shown in table 4?36 on page 4?20 and as reported by the timing analyzer in the quartus ii software. t m4kclr minimum clear pulse width table 4?42. m-ram block internal timing microparameter descriptions (part 1 of 2) symbol parameter t mramrc synchronous read cycle time t mramwc synchronous write cycle time t mramweresu write or read enable setup time before clock t mramwereh write or read enable hold time after clock t mramclkensu clock enable setup time before clock t mramclkenh clock enable hold time after clock t mrambesu byte enable setup time before clock t mrambeh byte enable hold time after clock t mramdataasu a port data setup time before clock t mramdataah a port data hold time after clock t mramaddrasu a port address setup time before clock t mramaddrah a port address hold time after clock t mramdatabsu b port setup time before clock table 4?41. m4k block internal timing microparameter descriptions (part 2 of 2) symbol parameter 4?26 altera corporation stratix device handbook, volume 1 july 2005 timing model t mramdatabh b port hold time after clock t mramaddrbsu b port address setup time before clock t mramaddrbh b port address hold time after clock t mramdataco1 clock-to-output delay when using output registers t mramdataco2 clock-to-output delay without output registers t mramclkhl register minimum clock high or low time. this is a limit on the min time for the clock on the registers in these blocks. the actual performance is dependent upon the internal point-to-point delays in the blocks and may give slower performance as shown in table 4?36 on page 4?20 and as reported by the timing analyzer in the quartus ii software. t mramclr minimum clear pulse width. table 4?42. m-ram block internal timing microparameter descriptions (part 2 of 2) symbol parameter altera corporation 4?27 july 2005 stratix device handbook, volume 1 dc & switching characteristics figure 4?3 shows the trimatrix memory waveforms for the m512, m4k, and m-ram timing parameters shown in tables 4?40 through 4?42 . figure 4?3. dual-port ram timi ng microparameter waveform internal timing parame ters are specified on a speed grade basis independent of device density. tables 4?44 through 4?50 show the internal timing microparameters for les, ioes, trimatrix memory structures, dsp blocks, and multitrack interconnects. wrclock wren wraddress data-in reg_data-out an-1 an a0 a1 a2 a3 a4 a5 din-1 din din4 din5 rdclock a6 din6 unreg_data-out rden rdaddress bn b0 b1 b2 b3 doutn-2 doutn-1 doutn doutn-1 doutn dout0 t weresu t wereh t datac o 1 t datac o 2 t datasu t data h t wereh t weresu t waddrsu t waddrh dout0 t rc table 4?43. routing delay internal timing microparameter descriptions (part 1 of 2) symbol parameter t r4 delay for an r4 line with average loading; covers a distance of four lab columns. t r8 delay for an r8 line with average lo ading; covers a distance of eight lab columns. t r24 delay for an r24 line with average loading; covers a distance of 24 lab columns. 4?28 altera corporation stratix device handbook, volume 1 july 2005 timing model t c4 delay for a c4 line with average loading; covers a distance of four lab rows. t c8 delay for a c8 line with average l oading; covers a distance of eight lab rows. t c16 delay for a c16 line with average loading; covers a distance of 16 lab rows. t local local interconnect delay, for connections within a lab, and for the final routing hop of connections to labs, dsp blocks, ram blocks and i/os. table 4?43. routing delay internal timing microparameter descriptions (part 2 of 2) symbol parameter table 4?44. le internal timing microparameters parameter -5 -6 -7 -8 unit min max min max min max min max t su 10 10 11 13 ps t h 100 100 114 135 ps t co 156 176 202 238 ps t lut 366 459 527 621 ps t clr 100 100 114 135 ps t pre 100 100 114 135 ps t clkhl 1000 1111 1190 1400 ps table 4?45. ioe internal tsu microparameter by device density (part 1 of 2) device symbol -5 -6 -7 -8 unit min max min max min max min max ep1s10 t su_r 76 80 80 80 ps t su_c 176 80 80 80 ps ep1s20 t su_r 76 80 80 80 ps t su_c 76 80 80 80 ps ep1s25 t su_r 276 280 280 280 ps t su_c 276 280 280 280 ps ep1s30 t su_r 76 80 80 80 ps t su_c 176 180 180 180 ps altera corporation 4?29 july 2005 stratix device handbook, volume 1 dc & switching characteristics ep1s40 t su_r 76 80 80 80 ps t su_c 376 380 380 380 ps ep1s60 t su_r 276 280 280 280 ps t su_c 276 280 280 280 ps ep1s80 t su_r 426 430 430 430 ps t su_c 76 80 80 80 ps table 4?46. ioe internal timing microparameters symbol -5 -6 -7 -8 unit min max min max min max min max t h 68 71 82 96 ps t co_r 171 179 206 242 ps t co_c 171 179 206 242 ps t pin2combout_r 1,234 1,295 1,490 1,753 ps t pin2combout_c 1,087 1,141 1,312 1,544 ps t combin2pin_r 3,894 4,089 4,089 4,089 ps t combin2pin_c 4,299 4,494 4,494 4,494 ps t clr 276 289 333 392 ps t pre 260 273 313 369 ps t clkhl 1,000 1,111 1,190 1,400 ps table 4?47. dsp block internal timing microparameters (part 1 of 2) symbol -5 -6 -7 -8 unit min max min max min max min max t su 0000ps t h 67 75 86 101 ps t co 142 158 181 214 ps t inreg2pipe9 2,613 2,982 3,429 4,035 ps t inreg2pipe18 3,390 3,993 4,591 5,402 ps table 4?45. ioe internal tsu microparameter by device density (part 2 of 2) device symbol -5 -6 -7 -8 unit min max min max min max min max 4?30 altera corporation stratix device handbook, volume 1 july 2005 timing model t pipe2outreg2add 2,002 2,203 2,533 2,980 ps t pipe2outreg4add 2,899 3,189 3,667 4,314 ps t pd9 3,709 4,081 4,692 5,520 ps t pd18 4,795 5,275 6,065 7,135 ps t pd36 7,495 8,245 9,481 11,154 ps t clr 450 500 575 676 ps t clkhl 1,350 1,500 1,724 2,029 ps table 4?48. m512 block internal timing microparameters symbol -5 -6 -7 -8 unit min max min max min max min max t m512rc 3,340 3,816 4,387 5,162 ps t m512wc 3,138 3,590 4,128 4,860 ps t m512weresu 110 123 141 166 ps t m512wereh 34 38 43 51 ps t m512clkensu 215 215 247 290 ps t m512clkenh ?70 ?70 ?81 ?95 ps t m512datasu 110 123 141 166 ps t m512datah 34 38 43 51 ps t m512waddrsu 110 123 141 166 ps t m512waddrh 34 38 43 51 ps t m512raddrsu 110 123 141 166 ps t m512raddrh 34 38 43 51 ps t m512dataco1 424 472 541 637 ps t m512dataco2 3,366 3,846 4,421 5,203 ps t m512clkhl 1,000 1,111 1,190 1,400 ps t m512clr 170 189 217 255 ps table 4?47. dsp block internal timing microparameters (part 2 of 2) symbol -5 -6 -7 -8 unit min max min max min max min max altera corporation 4?31 july 2005 stratix device handbook, volume 1 dc & switching characteristics table 4?49. m4k block internal timing microparameters symbol -5 -6 -7 -8 unit min max min max min max min max t m4krc 3,807 4,320 4,967 5,844 ps t m4kwc 2,556 2,840 3,265 3,842 ps t m4kweresu 131 149 171 202 ps t m4kwereh 34 38 43 51 ps t m4kclkensu 193 215 247 290 ps t m4kclkenh ?63 ?70 ?81 ?95 ps t m4kbesu 131 149 171 202 ps t m4kbeh 34 38 43 51 ps t m4kdataasu 131 149 171 202 ps t m4kdataah 34 38 43 51 ps t m4kaddrasu 131 149 171 202 ps t m4kaddrah 34 38 43 51 ps t m4kdatabsu 131 149 171 202 ps t m4kdatabh 34 38 43 51 ps t m4kaddrbsu 131 149 171 202 ps t m4kaddrbh 34 38 43 51 ps t m4kdataco1 571 635 729 858 ps t m4kdataco2 3,984 4,507 5,182 6,097 ps t m4kclkhl 1,000 1,111 1,190 1,400 ps t m4kclr 170 189 217 255 ps table 4?50. m-ram block internal ti ming microparameters (part 1 of 2) symbol -5 -6 -7 -8 unit min max min max min max min max t mramrc 4,364 4,838 5,562 6,544 ps t mramwc 3,654 4,127 4,746 5,583 ps t mramweresu 25 25 28 33 ps t mramwereh 18 20 23 27 ps t mramclkensu 99 111 127 150 ps t mramclkenh ?48 ?53 ?61 ?72 ps 4?32 altera corporation stratix device handbook, volume 1 july 2005 timing model routing delays vary depending on the load on that specific routing line. the quartus ii software reports th e routing delay information when running the timing analysis for a design. t mrambesu 25 25 28 33 ps t mrambeh 18 20 23 27 ps t mramdataasu 25 25 28 33 ps t mramdataah 18 20 23 27 ps t mramaddrasu 25 25 28 33 ps t mramaddrah 18 20 23 27 ps t mramdatabsu 25 25 28 33 ps t mramdatabh 18 20 23 27 ps t mramaddrbsu 25 25 28 33 ps t mramaddrbh 18 20 23 27 ps t mramdataco1 1,038 1,053 1,210 1,424 ps t mramdataco2 4,362 4,939 5,678 6,681 ps t mramclkhl 1,000 1,111 1,190 1,400 ps t mramclr 135 150 172 202 ps table 4?51. routing delay internal timing parameters symbol -5 -6 -7 -8 unit min max min max min max min max t r4 268 295 339 390 ps t r8 371 349 401 461 ps t r24 465 512 588 676 ps t c4 440 484 557 641 ps t c8 577 634 730 840 ps t c16 445 489 563 647 ps t local 313 345 396 455 ps table 4?50. m-ram block internal ti ming microparameters (part 2 of 2) symbol -5 -6 -7 -8 unit min max min max min max min max altera corporation 4?33 july 2005 stratix device handbook, volume 1 dc & switching characteristics external timing parameters external timing parameters are specified by device density and speed grade. figure 4?4 shows the pin-to-pin timing model for bidirectional ioe pin timing. all registers are within the ioe. figure 4?4. external timing in stratix devices all external timing parameters report ed in this section are defined with respect to the dedicated clock pin as th e starting point. all external i/o timing parameters shown are for 3. 3-v lvttl i/o standard with the 24-ma current strength and fast slew rate. for external i/o timing using standards other than lvttl or for diff erent current strengths, use the i/o standard input and output delay adders in tables 4?103 through 4?108 . prn clrn dq oe re g ister prn clrn dq input re g ister prn clrn dq output re g ister bidirectional pin dedicated clock t in su t inh t ou t co t xz t zx 4?34 altera corporation stratix device handbook, volume 1 july 2005 timing model table 4?52 shows the external i/o timing parameters when using fast regional clock networks. table 4?53 shows the external i/o timing parameters when using regional clock networks. table 4?52. stratix fast regional clock external i/o timing parameters notes (1) , (2) symbol parameter t insu setup time for input or bidirectiona l pin using ioe input register with fast regional clock fed by fclk pin t inh hold time for input or bidirectional pin using ioe input register with fast regional clock fed by fclk pin t outco clock-to-output delay output or bi directional pin using ioe output register with fast regional clock fed by fclk pin t xz synchronous ioe output enab le register to output pin disable delay using fast regional clock fed by fclk pin t zx synchronous ioe output enab le register to output pin enable delay using fast regional clock fed by fclk pin notes to ta b l e 4 ? 5 2 : (1) these timing parameters are sample-tested only. (2) these timing parameters are for column and row ioe pins. you should use the quartus ii software to verify the external timing for any pin. table 4?53. stratix regional clock exte rnal i/o timing parameters (part 1 of 2) notes (1) , (2) symbol parameter t insu setup time for input or bidirectional pin using ioe input register with regional clock fed by clk pin t inh hold time for input or bidirectional pin using ioe input register with regional clock fed by clk pin t outco clock-to-output delay output or bi directional pin using ioe output register with regional clock fed by clk pin t insupll setup time for input or bidirectional pin using ioe input register with regional clock fed by enhanced pll with default phase setting t inhpll hold time for input or bidirectional pin using ioe input register with regional clock fed by enhanced pll with default phase setting t outcopll clock-to-output delay output or bi directional pin using ioe output register with regional clock e nhanced pll with default phase setting altera corporation 4?35 july 2005 stratix device handbook, volume 1 dc & switching characteristics table 4?54 shows the external i/o timing parameters when using global clock networks. t xzpll synchronous ioe output enable regist er to output pin disable delay using regional clock fed by enhanc ed pll with default phase setting t zxpll synchronous ioe output enable regi ster to output pin enable delay using regional clock fed by enhanc ed pll with default phase setting notes to ta b l e 4 ? 5 3 : (1) these timing parameters are sample-tested only. (2) these timing parameters are for column and row ioe pins. you should use the quartus ii software to verify the external timing for any pin. table 4?54. stratix global clock ex ternal i/o timing parameters notes (1) , (2) symbol parameter t insu setup time for input or bidirectional pin using ioe input register with global clock fed by clk pin t inh hold time for input or bidirectional pin using ioe input register with global clock fed by clk pin t outco clock-to-output delay output or bi directional pin using ioe output register with global clock fed by clk pin t insupll setup time for input or bidirectional pin using ioe input register with global clock fed by enhanced pll with default phase setting t inhpll hold time for input or bidirectional pin using ioe input register with global clock fed by enhanced pll with default phase setting t outcopll clock-to-output delay output or bi directional pin using ioe output register with global clock enhanced pll with default phase setting t xzpll synchronous ioe output enab le register to output pin disable delay using global clock fed by enhanced pll with default phase setting t zxpll synchronous ioe output enab le register to output pin enable delay using global clock fed by enhanced pll with default phase setting notes to ta b l e 4 ? 5 4 : (1) these timing parameters are sample-tested only. (2) these timing parameters are for column and row ioe pins. you should use the quartus ii software to verify the external timing for any pin. table 4?53. stratix regional clock exte rnal i/o timing parameters (part 2 of 2) notes (1) , (2) symbol parameter 4?36 altera corporation stratix device handbook, volume 1 july 2005 timing model stratix external i/o timing these timing parameters are for both column ioe and row ioe pins. in ep1s30 devices and above, you can decrease the t su time by using the fpllclk , but may get positive hold time in ep1s60 and ep1s80 devices. you should use the quartus ii software to verify the external devices for any pin. tables 4?55 through 4?60 show the external timing parameters on column and row pins for ep1s10 devices. table 4?55. ep1s10 external i/o timing on column pins using fast regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmax min max t insu 2.238 2.325 2.668 na ns t inh 0.000 0.000 0.000 na ns t outco 2.240 4.549 2.240 4.836 2.240 5.218 na na ns t xz 2.180 4.423 2.180 4.704 2.180 5.094 na na ns t zx 2.180 4.423 2.180 4.704 2.180 5.094 na na ns table 4?56. ep1s10 external i/o timing on colu mn pins using regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t insu 1.992 2.054 2.359 na ns t inh 0.000 0.000 0.000 na ns t outco 2.395 4.795 2.395 5.107 2.395 5.527 na na ns t xz 2.335 4.669 2.335 4.975 2.335 5.403 na na ns t zx 2.335 4.669 2.335 4.975 2.335 5.403 na na ns t insupll 0.975 0.985 1.097 na ns t inhpll 0.000 0.000 0.000 na na ns t outcopll 1.262 2.636 1.262 2.680 1.262 2.769 na na ns t xzpll 1.202 2.510 1.202 2.548 1.202 2.645 na na ns t zxpll 1.202 2.510 1.202 2.548 1.202 2.645 na na ns altera corporation 4?37 july 2005 stratix device handbook, volume 1 dc & switching characteristics table 4?57. ep1s10 external i/o timing on co lumn pins using global clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.647 1.692 1.940 na ns t inh 0.000 0.000 0.000 na ns t outco 2.619 5.184 2.619 5.515 2.619 5.999 na na ns t xz 2.559 5.058 2.559 5.383 2.559 5.875 na na ns t zx 2.559 5.058 2.559 5.383 2.559 5.875 na na ns t insupll 1.239 1.229 1.374 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.109 2.372 1.109 2.436 1.109 2.492 na na ns t xzpll 1.049 2.246 1.049 2.304 1.049 2.368 na na ns t zxpll 1.049 2.246 1.049 2.304 1.049 2.368 na na ns table 4?58. ep1s10 external i/o timing on ro w pin using fast regional clock network note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 2.212 2.403 2.759 na ns t inh 0.000 0.000 0.000 na ns t outco 2.391 4.838 2.391 5.159 2.391 5.569 na na ns t xz 2.418 4.892 2.418 5.215 2.418 5.637 na na ns t zx 2.418 4.892 2.418 5.215 2.418 5.637 na na ns 4?38 altera corporation stratix device handbook, volume 1 july 2005 timing model table 4?59. ep1s10 external i/o timing on ro w pins using regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 2.161 2.336 2.685 na ns t inh 0.000 0.000 0.000 na ns t outco 2.434 4.889 2.434 5.226 2.434 5.643 na na ns t xz 2.461 4.493 2.461 5.282 2.461 5.711 na na ns t zx 2.461 4.493 2.461 5.282 2.461 5.711 na na ns t insupll 1.057 1.172 1.315 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.327 2.773 1.327 2.848 1.327 2.940 na na ns t xzpll 1.354 2.827 1.354 2.904 1.354 3.008 na na ns t zxpll 1.354 2.827 1.354 2.904 1.354 3.008 na na ns table 4?60. ep1s10 external i/o timing on row pins using global clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.787 1.944 2.232 na ns t inh 0.000 0.000 0.000 na ns t outco 2.647 5.263 2.647 5.618 2.647 6.069 na na ns t xz 2.674 5.317 2.674 5.674 2.674 6.164 na na ns t zx 2.674 5.317 2.674 5.674 2.674 6.164 na na ns t insupll 1.371 1.1472 1.654 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.144 2.459 1.144 2.548 1.144 2.601 na na ns t xzpll 1.171 2.513 1.171 2.604 1.171 2.669 na na ns t zxpll 1.171 2.513 1.171 2.604 1.171 2.669 na na ns note to tables 4?55 to 4?60 : (1) only ep1s25, ep1s30, and ep1s40 have speed grade of -8. altera corporation 4?39 july 2005 stratix device handbook, volume 1 dc & switching characteristics tables 4?61 through 4?66 show the external timing parameters on column and row pins for ep1s20 devices. table 4?61. ep1s20 external i/o timing on column pins using fast regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.065 2.245 2.576 na ns t inh 0.000 0.000 0.000 na ns t outco 2.283 4.622 2.283 4.916 2.283 5.310 na na ns t xz 2.223 4.496 2.223 4.784 2.223 5.186 na na ns t zx 2.223 4.496 2.223 4.784 2.223 5.186 na na ns table 4?62. ep1s20 external i/o timing on colu mn pins using regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.541 1.680 1.931 na ns t inh 0.000 0.000 0.000 na ns t outco 2.597 5.146 2.597 5.481 2.597 5.955 na na ns t xz 2.537 5.020 2.537 5.349 2.537 5.831 na na ns t zx 2.537 5.020 2.537 5.349 2.537 5.831 na na ns t insupll 0.777 0.818 0.937 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.296 2.690 1.296 2.801 1.296 2.876 na na ns t xzpll 1.236 2.564 1.236 2.669 1.236 2.752 na na ns t zxpll 1.236 2.564 1.236 2.669 1.236 2.752 na na ns 4?40 altera corporation stratix device handbook, volume 1 july 2005 timing model table 4?63. ep1s20 external i/o timing on co lumn pins using global clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 1.351 1.479 1.699 na ns t inh 0.000 0.000 0.000 na ns t outco 2.732 5.380 2.732 5.728 2.732 6.240 na na ns t xz 2.672 5.254 2.672 5.596 2.672 6.116 na na ns t zx 2.672 5.254 2.672 5.596 2.672 6.116 na na ns t insupll 0.923 0.971 1.098 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.210 2.544 1.210 2.648 1.210 2.715 na na ns t xzpll 1.150 2.418 1.150 2.516 1.150 2.591 na na ns t zxpll 1.150 2.418 1.150 2.516 1.150 2.591 na na ns table 4?64. ep1s20 external i/o timing on row pins using fast regi onal clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.032 2.207 2.535 na ns t inh 0.000 0.000 0.000 na ns t outco 2.492 5.018 2.492 5.355 2.492 5.793 na na ns t xz 2.519 5.072 2.519 5.411 2.519 5.861 na na ns t zx 2.519 5.072 2.519 5.411 2.519 5.861 na na ns altera corporation 4?41 july 2005 stratix device handbook, volume 1 dc & switching characteristics table 4?65. ep1s20 external i/o timing on ro w pins using regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.815 1.967 2.258 na ns t inh 0.000 0.000 0.000 na ns t outco 2.633 5.235 2.663 5.595 2.663 6.070 na na ns t xz 2.660 5.289 2.660 5.651 2.660 6.138 na na ns t zx 2.660 5.289 2.660 5.651 2.660 6.138 na na ns t insupll 1.060 1.112 1.277 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.325 2.770 1.325 2.908 1.325 2.978 na na ns t xzpll 1.352 2.824 1.352 2.964 1.352 3.046 na na ns t zxpll 1.352 2.824 1.352 2.964 1.352 3.046 na na ns table 4?66. ep1s20 external i/o timing on row pins using global clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.742 1.887 2.170 na ns t inh 0.000 0.000 0.000 na ns t outco 2.674 5.308 2.674 5.675 2.674 6.158 na na ns t xz 2.701 5.362 2.701 5.731 2.701 6.226 na na ns t zx 2.701 5.362 2.701 5.731 2.701 6.226 na na ns t insupll 1.353 1.418 1.613 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.158 2.447 1.158 2.602 1.158 2.642 na na ns t xzpll 1.185 2.531 1.158 2.602 1.185 2.710 na na ns t zxpll 1.185 2.531 1.158 2.602 1.185 2.710 na na ns note to tables 4?61 to 4?66 : (1) only ep1s25, ep1s30, and ep1s40 have a speed grade of -8. 4?42 altera corporation stratix device handbook, volume 1 july 2005 timing model tables 4?67 through 4?72 show the external timing parameters on column and row pins for ep1s25 devices. table 4?67. ep1s25 external i/o timing on colu mn pins using fast regional clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.412 2.613 2.968 3.468 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.196 4.475 2.196 4.748 2.196 5.118 2.196 5.603 ns t xz 2.136 4.349 2.136 4.616 2.136 4.994 2.136 5.488 ns t zx 2.136 4.349 2.136 4.616 2.136 4.994 2.136 5.488 ns table 4?68. ep1s25 external i/o timing on co lumn pins using regional clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.535 1.661 1.877 2.125 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.739 5.396 2.739 5.746 2.739 6.262 2.739 6.946 ns t xz 2.679 5.270 2.679 5.614 2.679 6.138 2.679 6.831 ns t zx 2.679 5.270 2.679 5.614 2.679 6.138 2.679 6.831 ns t insupll 0.934 0.980 1.092 1.231 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.316 2.733 1.316 2.839 1.316 2.921 1.316 3.110 ns t xzpll 1.256 2.607 1.256 2.707 1.256 2.797 1.256 2.995 ns t zxpll 1.256 2.607 1.256 2.707 1.256 2.797 1.256 2.995 ns altera corporation 4?43 july 2005 stratix device handbook, volume 1 dc & switching characteristics table 4?69. ep1s25 external i/o timing on co lumn pins using global clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 1.371 1.471 1.657 1.916 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.809 5.516 2.809 5.890 2.809 6.429 2.809 7.155 ns t xz 2.749 5.390 2.749 5.758 2.749 6.305 2.749 7.040 ns t zx 2.749 5.390 2.749 5.758 2.749 6.305 2.749 7.040 ns t insupll 1.271 1.327 1.491 1.677 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.124 2.396 1.124 2.492 1.124 2.522 1.124 2.602 ns t xzpll 1.064 2.270 1.064 2.360 1.064 2.398 1.064 2.487 ns t zxpll 1.064 2.270 1.064 2.360 1.064 2.398 1.064 2.487 ns table 4?70. ep1s25 external i/o timing on ro w pins using fast r egional clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 2.429 2.631 2.990 3.503 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.376 4.821 2.376 5.131 2.376 5.538 2.376 6.063 ns t xz 2.403 4.875 2.403 5.187 2.403 5.606 2.403 6.145 ns t zx 2.403 4.875 2.403 5.187 2.403 5.606 2.403 6.145 ns 4?44 altera corporation stratix device handbook, volume 1 july 2005 timing model table 4?71. ep1s25 external i/o timing on row pins using regi onal clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.793 1.927 2.182 2.542 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.759 5.457 2.759 5.835 2.759 6.346 2.759 7.024 ns t xz 2.786 5.511 2.786 5.891 2.786 6.414 2.786 7.106 ns t zx 2.786 5.511 2.786 5.891 2.786 6.414 2.786 7.106 ns t insupll 1.169 1.221 1.373 1.600 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.375 2.861 1.375 2.999 1.375 3.082 1.375 3.174 ns t xzpll 1.402 2.915 1.402 3.055 1.402 3.150 1.402 3.256 ns t zxpll 1.402 2.915 1.402 3.055 1.402 3.150 1.402 3.256 ns table 4?72. ep1s25 external i/o timing on row pins using global clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.665 1.779 2.012 2.372 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.834 5.585 2.834 5.983 2.834 6.516 2.834 7.194 ns t xz 2.861 5.639 2.861 6.039 2.861 6.584 2.861 7.276 ns t zx 2.861 5.639 2.861 6.039 2.861 6.584 2.861 7.276 ns t insupll 1.538 1.606 1.816 2.121 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.164 2.492 1.164 2.614 1.164 2.639 1.164 2.653 ns t xzpll 1.191 2.546 1.191 2.670 1.191 2.707 1.191 2.735 ns t zxpll 1.191 2.546 1.191 2.670 1.191 2.707 1.191 2.735 ns altera corporation 4?45 july 2005 stratix device handbook, volume 1 dc & switching characteristics tables 4?73 through 4?78 show the external timing parameters on column and row pins for ep1s30 devices. table 4?73. ep1s30 external i/o timing on colu mn pins using fast regional clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 2.502 2.680 3.062 3.591 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.473 4.965 2.473 5.329 2.473 5.784 2.473 6.392 ns t xz 2.413 4.839 2.413 5.197 2.413 5.660 2.413 6.277 ns t zx 2.413 4.839 2.413 5.197 2.413 5.660 2.413 6.277 ns table 4?74. ep1s30 external i/o timing on colu mn pins using regional clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.286 2.426 2.769 3.249 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.641 5.225 2.641 5.629 2.641 6.130 2.641 6.796 ns t xz 2.581 5.099 2.581 5.497 2.581 6.006 2.581 6.681 ns t zx 2.581 5.099 2.581 5.497 2.581 6.006 2.581 6.681 ns t insupll 1.200 1.185 1.344 1.662 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.108 2.367 1.108 2.534 1.108 2.569 1.108 2.517 ns t xzpll 1.048 2.241 1.048 2.402 1.048 2.445 1.048 2.402 ns t zxpll 1.048 2.241 1.048 2.402 1.048 2.445 1.048 2.402 ns table 4?75. ep1s30 external i/o timing on column pins using global clock networks (part 1 of 2) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.935 2.029 2.310 2.709 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.814 5.532 2.814 5.980 2.814 6.536 2.814 7.274 ns 4?46 altera corporation stratix device handbook, volume 1 july 2005 timing model t xz 2.754 5.406 2.754 5.848 2.754 6.412 2.754 7.159 ns t zx 2.754 5.406 2.754 5.848 2.754 6.412 2.754 7.159 ns t insupll 1.265 1.236 1.403 1.756 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.068 2.302 1.068 2.483 1.068 2.510 1.068 2.423 ns t xzpll 1.008 2.176 1.008 2.351 1.008 2.386 1.008 2.308 ns t zxpll 1.008 2.176 1.008 2.351 1.008 2.386 1.008 2.308 ns table 4?76. ep1s30 external i/o timing on ro w pins using fast r egional clock networks parameters -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.616 2.808 3.223 3.797 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.542 5.114 2.542 5.502 2.542 5.965 2.542 6.581 ns t xz 2.569 5.168 2.569 5.558 2.569 6.033 2.569 6.663 ns t zx 2.569 5.168 2.569 5.558 2.569 6.033 2.569 6.663 ns table 4?75. ep1s30 external i/o timing on column pins using global clock networks (part 2 of 2) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax altera corporation 4?47 july 2005 stratix device handbook, volume 1 dc & switching characteristics table 4?77. ep1s30 external i/o timing on row pins using regi onal clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.322 2.467 2.828 3.342 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.731 5.408 2.731 5.843 2.731 6.360 2.731 7.036 ns t xz 2.758 5.462 2.758 5.899 2.758 6.428 2.758 7.118 ns t zx 2.758 5.462 2.758 5.899 2.758 6.428 2.758 7.118 ns t insupll 1.291 1.283 1.469 1.832 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.192 2.539 1.192 2.737 1.192 2.786 1.192 2.742 ns t xzpll 1.219 2.539 1.219 2.793 1.219 2.854 1.219 2.824 ns t zxpll 1.219 2.539 1.219 2.793 1.219 2.854 1.219 2.824 ns table 4?78. ep1s30 external i/o timing on row pins using global clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 1.995 2.089 2.398 2.830 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.917 5.735 2.917 6.221 2.917 6.790 2.917 7.548 ns t xz 2.944 5.789 2.944 6.277 2.944 6.858 2.944 7.630 ns t zx 2.944 5.789 2.944 6.277 2.944 6.858 2.944 7.630 ns t insupll 1.337 1.312 1.508 1.902 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.164 2.493 1.164 2.708 1.164 2.747 1.164 2.672 ns t xzpll 1.191 2.547 1.191 2.764 1.191 2.815 1.191 2.754 ns t zxpll 1.191 2.547 1.191 2.764 1.191 2.815 1.191 2.754 ns 4?48 altera corporation stratix device handbook, volume 1 july 2005 timing model tables 4?79 through 4?84 show the external timing parameters on column and row pins for ep1s40 devices. table 4?79. ep1s40 external i/o timing on colu mn pins using fast regional clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.696 2.907 3.290 2.899 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.506 5.015 2.506 5.348 2.506 5.809 2.698 7.286 ns t xz 2.446 4.889 2.446 5.216 2.446 5.685 2.638 7.171 ns t zx 2.446 4.889 2.446 5.216 2.446 5.685 2.638 7.171 ns table 4?80. ep1s40 external i/o timing on co lumn pins using regional clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.413 2.581 2.914 2.938 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.668 5.254 2.668 5.628 2.668 6.132 2.869 7.307 ns t xz 2.608 5.128 2.608 5.496 2.608 6.008 2.809 7.192 ns t zx 2.608 5.128 2.608 5.496 2.608 6.008 2.809 7.192 ns t insupll 1.385 1.376 1.609 1.837 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.117 2.382 1.117 2.552 1.117 2.504 1.117 2.542 ns t xzpll 1.057 2.256 1,057 2.420 1.057 2.380 1.057 2.427 ns t zxpll 1.057 2.256 1,057 2.420 1.057 2.380 1.057 2.427 ns altera corporation 4?49 july 2005 stratix device handbook, volume 1 dc & switching characteristics table 4?81. ep1s40 external i/o timing on co lumn pins using global clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.126 2.268 2.558 2.930 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.856 5.585 2.856 5.987 2.856 6.541 2.847 7.253 ns t xz 2.796 5.459 2.796 5.855 2.796 6.417 2.787 7.138 ns t zx 2.796 5.459 2.796 5.855 2.796 6.417 2.787 7.138 ns t insupll 1.466 1.455 1.711 1.906 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.092 2.345 1.092 2.510 1.092 2.455 1.089 2.473 ns t xzpll 1.032 2.219 1.032 2.378 1.032 2.331 1.029 2.358 ns t zxpll 1.032 2.219 1.032 2.378 1.032 2.331 1.029 2.358 ns table 4?82. ep1s40 external i/o timing on ro w pins using fast r egional clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.472 2.685 3.083 3.056 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.631 5.258 2.631 5.625 2.631 6.105 2.745 7.324 ns t xz 2.658 5.312 2.658 5.681 2.658 6.173 2.772 7.406 ns t zx 2.658 5.312 2.658 5.681 2.658 6.173 2.772 7.406 ns 4?50 altera corporation stratix device handbook, volume 1 july 2005 timing model table 4?83. ep1s40 external i/o timing on row pins using regi onal clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 2.349 2.526 2.898 2.952 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.725 5.381 2.725 5.784 2.725 6.290 2.725 7.426 ns t xz 2.752 5.435 2.752 5.840 2.752 6.358 2.936 7.508 ns t zx 2.752 5.435 2.752 5.840 2.752 6.358 2.936 7.508 ns t insupll 1.328 1.322 1.605 1.883 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.169 2.502 1.169 2.698 1.169 2.650 1.169 2.691 ns t xzpll 1.196 2.556 1.196 2.754 1.196 2.718 1.196 2.773 ns t zxpll 1.196 2.556 1.196 2.754 1.196 2.718 1.196 2.773 ns table 4?84. ep1s40 external i/o timing on row pins using global clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 2.020 2.171 2.491 2.898 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.912 5.710 2.912 6.139 2.912 6.697 2.931 7.480 ns t xz 2.939 5.764 2.939 6.195 2.939 6.765 2.958 7.562 ns t zx 2.939 5.764 2.939 6.195 2.939 6.765 2.958 7.562 ns t insupll 1.370 1.368 1.654 1.881 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.144 2.460 1.144 2.652 1.144 2.601 1.170 2.693 ns t xzpll 1.171 2.514 1.171 2.708 1.171 2.669 1.197 2.775 ns t zxpll 1.171 2.514 1.171 2.708 1.171 2.669 1.197 2.775 ns altera corporation 4?51 july 2005 stratix device handbook, volume 1 dc & switching characteristics tables 4?85 through 4?90 show the external timing parameters on column and row pins for ep1s60 devices. table 4?85. ep1s60 external i/o timing on column pins using fast regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 3.029 3.277 3.733 na ns t inh 0.000 0.000 0.000 na ns t outco 2.446 4.871 2.446 5.215 2.446 5.685 na na ns t xz 2.386 4.745 2.386 5.083 2.386 5.561 na na ns t zx 2.386 4.745 2.386 5.083 2.386 5.561 na na ns table 4?86. ep1s60 external i/o timing on colu mn pins using regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.491 2.691 3.060 na ns t inh 0.000 0.000 0.000 na ns t outco 2.767 5.409 2.767 5.801 2.767 6.358 na na ns t xz 2.707 5.283 2.707 5.669 2.707 6.234 na na ns t zx 2.707 5.283 2.707 5.669 2.707 6.234 na na ns t insupll 1.233 1.270 1.438 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.078 2.278 1.078 2.395 1.078 2.428 na na ns t xzpll 1.018 2.152 1.018 2.263 1.018 2.304 na na ns t zxpll 1.018 2.152 1.018 2.263 1.018 2.304 na na ns 4?52 altera corporation stratix device handbook, volume 1 july 2005 timing model table 4?87. ep1s60 external i/o timing on co lumn pins using global clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 2.000 2.152 2.441 na ns t inh 0.000 0.000 0.000 na ns t outco 3.051 5.900 3.051 6.340 3.051 6.977 na na ns t xz 2.991 5.774 2.991 6.208 2.991 6.853 na na ns t zx 2.991 5.774 2.991 6.208 2.991 6.853 na na ns t insupll 1.315 1.362 1.543 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.029 2.196 1.029 2.303 1.029 2.323 na na ns t xzpll 0.969 2.070 0.969 2.171 0.969 2.199 na na ns t zxpll 0.969 2.070 0.969 2.171 0.969 2.199 na na ns table 4?88. ep1s60 external i/o timing on row pins using fast regi onal clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 3.144 3.393 3.867 na ns t inh 0.000 0.000 0.000 na ns t outco 2.643 5.275 2.643 5.654 2.643 6.140 na na ns t xz 2.670 5.329 2.670 5.710 2.670 6.208 na na ns t zx 2.670 5.329 2.670 5.710 2.670 6.208 na na ns altera corporation 4?53 july 2005 stratix device handbook, volume 1 dc & switching characteristics table 4?89. ep1s60 external i/o timing on ro w pins using regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.775 2.990 3.407 na ns t inh 0.000 0.000 0.000 na ns t outco 2.867 5.644 2.867 6.057 2.867 6.600 na na ns t xz 2.894 5.698 2.894 6.113 2.894 6.668 na na ns t zx 2.894 5.698 2.894 6.113 2.894 6.668 na na ns t insupll 1.523 1.577 1.791 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.174 2.507 1.174 2.643 1.174 2.664 na na ns t xzpll 1.201 2.561 1.201 2.699 1.201 2.732 na na ns t zxpll 1.201 2.561 1.201 2.699 1.201 2.732 na na ns table 4?90. ep1s60 external i/o timing on row pins using global clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.232 2.393 2.721 na ns t inh 0.000 0.000 0.000 na ns t outco 3.182 6.187 3.182 6.654 3.182 7.286 na na ns t xz 3.209 6.241 3.209 6.710 3.209 7.354 na na ns t zx 3.209 6.241 3.209 6.710 3.209 7.354 na na ns t insupll 1.651 1.612 1.833 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.154 2.469 1.154 2.608 1.154 2.622 na na ns t xzpll 1.181 2.523 1.181 2.664 1.181 2.690 na na ns t zxpll 1.181 2.523 1.181 2.664 1.181 2.690 na na ns note to tables 4?85 to 4?90 : (1) only ep1s25, ep1s30, and ep1s40 devices have the -8 speed grade. 4?54 altera corporation stratix device handbook, volume 1 july 2005 timing model tables 4?91 through 4?96 show the external timing parameters on column and row pins for ep1s80 devices. table 4?91. ep1s80 external i/o timing on column pins using fast regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.328 2.528 2.900 na ns t inh 0.000 0.000 0.000 na ns t outco 2.422 4.830 2.422 5.169 2.422 5.633 na na ns t xz 2.362 4.704 2.362 5.037 2.362 5.509 na na ns t zx 2.362 4.704 2.362 5.037 2.362 5.509 na na ns table 4?92. ep1s80 external i/o timing on colu mn pins using regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.760 1.912 2.194 na ns t inh 0.000 0.000 0.000 na ns t outco 2.761 5.398 2.761 5.785 2.761 6.339 na na ns t xz 2.701 5.272 2.701 5.653 2.701 6.215 na na ns t zx 2.701 5.272 2.701 5.653 2.701 6.215 na na ns t insupll 0.462 0.606 0.785 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.661 2.849 1.661 2.859 1.661 2.881 na na ns t xzpll 1.601 2.723 1.601 2.727 1.601 2.757 na na ns t zxpll 1.601 2.723 1.601 2.727 1.601 2.757 na na ns altera corporation 4?55 july 2005 stratix device handbook, volume 1 dc & switching characteristics table 4?93. ep1s80 external i/o timing on co lumn pins using global clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 0.884 0.976 1.118 na ns t inh 0.000 0.000 0.000 na ns t outco 3.267 6.274 3.267 6.721 3.267 7.415 na na ns t xz 3.207 6.148 3.207 6.589 3.207 7.291 na na ns t zx 3.207 6.148 3.207 6.589 3.207 7.291 na na ns t insupll 0.506 0.656 0.838 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.635 2.805 1.635 2.809 1.635 2.828 na na ns t xzpll 1.575 2.679 1.575 2.677 1.575 2.704 na na ns t zxpll 1.575 2.679 1.575 2.677 1.575 2.704 na na ns table 4?94. ep1s80 external i/o timing on row pins using fast regi onal clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.792 2.993 3.386 na ns t inh 0.000 0.000 0.000 na ns t outco 2.619 5.235 2.619 5.609 2.619 6.086 na na ns t xz 2.646 5.289 2.646 5.665 2.646 6.154 na na ns t zx 2.646 5.289 2.646 5.665 2.646 6.154 na na ns 4?56 altera corporation stratix device handbook, volume 1 july 2005 timing model table 4?95. ep1s80 external i/o timing on ro w pins using regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.295 2.454 2.767 na ns t inh 0.000 0.000 0.000 na ns t outco 2.917 5.732 2.917 6.148 2.917 6.705 na na ns t xz 2.944 5.786 2.944 6.204 2.944 6.773 na na ns t zx 2.944 5.786 2.944 6.204 2.944 6.773 na na ns t insupll 1.011 1.161 1.372 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.808 3.169 1.808 3.209 1.808 3.233 na na ns t xzpll 1.835 3.223 1.835 3.265 1.835 3.301 na na ns t zxpll 1.835 3.223 1.835 3.265 1.835 3.301 na na ns table 4?96. ep1s80 external i/o timing on rows using pin global clock networks note (1) symbol -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.362 1.451 1.613 na ns t inh 0.000 0.000 0.000 na ns t outco 3.457 6.665 3.457 7.151 3.457 7.859 na na ns t xz 3.484 6.719 3.484 7.207 3.484 7.927 na na ns t zx 3.484 6.719 3.484 7.207 3.484 7.927 na na ns t insupll o.994 1.143 1.351 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.821 3.186 1.821 3.227 1.821 3.254 na na ns t xzpll 1.848 3.240 1.848 3.283 1.848 3.322 na na ns t zxpll 1.848 3.240 1.848 3.283 1.848 3.322 na na ns note to tables 4?91 to 4?96 : (1) only ep1s25, ep1s30, and ep1s40 devices have the -8 speed grade. altera corporation 4?57 july 2005 stratix device handbook, volume 1 dc & switching characteristics definition of i/o skew i/o skew is defined as the absolute va lue of the worst-case difference in clock-to-out times (t co ) between any two output registers fed by a common clock source. i/o bank skew is made up of the following components: clock network skews: this is the difference between the arrival times of the clock at the clock input port of the two ioe registers. package skews: this is the packag e trace length differences between (i/o pad a to i/o pin a) and (i/o pad b to i/o pin b). figure 4?5 shows an example of two ioe registers located in the same bank, being fed by a common clock source. the clock can come from an input pin or from a pll output. figure 4?5. i/o skew within an i/o bank common source of gclk fast edge slow edge i/o skew i/o bank i/o skew i/o pin a i/o pin b i/o pin a i/o pin b 4?58 altera corporation stratix device handbook, volume 1 july 2005 timing model figure 4?6 shows the case where four ioe registers are located in two different i/o banks. figure 4?6. i/o skew ac ross two i/o banks table 4?97 defines the timing parameters used to define the timing for horizontal i/o pins (side banks 1, 2, 5, 6) and vertical i/o pins (top and bottom banks 3, 4, 7, 8). the timing pa rameters define the skew within an i/o bank, across two neighboring i /o banks on the same side of the device, across all horizont al i/o banks, ac ross all vertical i/o banks, and the skew for the overall device. table 4?97. output pin timing skew definitions (part 1 of 2) symbol definition t sb_hio row i/o (hio) within one i/o bank (1) t sb_vio column i/o (vio) within one i/o bank (1) t ss_hio row i/o (hio) same side of the device, across two banks (2) t ss_vio column i/o (vio) same side of the device, across two banks (2) common source of gclk i/o bank i/o bank i/o pin a i/o pin b i/o pin c i/o pin d i/o pin a i/o pin b i/o pin c i/o pin d i/o pin skew across two banks altera corporation 4?59 july 2005 stratix device handbook, volume 1 dc & switching characteristics table 4?98 shows the i/o skews when using the same global or regional clock to feed ioe registers in i/o banks around each device. these values can be used for calculating the timing budget on the output (write) side of a memory interface. these values already factor in the package skew. t lr_hio across all hio banks (1, 2, 5, 6); across four similar type i/o banks t tb_vio across all vio banks (3, 4, 7, 8); across four similar type i/o banks t overall output timing skew for all i/o pins on the device. notes to ta b l e 4 ? 9 7 : (1) see figure 4?5 on page 4?57 . (2) see figure 4?6 on page 4?58 . table 4?98. output skew for stratix by device density symbol skew (ps) (1) ep1s10 to ep1s30 ep1s40 ep1s60 & ep1s80 t sb_hio 90 290 500 t sb_vio 160 290 500 t ss_hio 90 460 600 t ss_vio 180 520 630 t lr_hio 150 490 600 t tb_vio 190 580 670 t overall 430 630 880 note to table 4?98 : (1) the skew numbers in table 4?98 account for worst case package skews. table 4?97. output pin timing skew definitions (part 2 of 2) symbol definition 4?60 altera corporation stratix device handbook, volume 1 july 2005 timing model skew on input pins table 4?99 shows the package skews that were considered to get the worst case i/o skew value. you can use these values, for example, when calculating the timing budget on the input (read) side of a memory interface. pll counter & clock network skews table 4?100 shows the clock skews between different clock outputs from the stratix device pll. i/o timing measurement methodology different i/o standards require different baseline loading techniques for reporting timing delays. altera char acterizes timing delays with the required termination and loading fo r each i/o standard. the timing information is specified from the inpu t clock pin up to the output pin of table 4?99. package skew on input pins package parameter worst-case skew (ps) pins in the same i/o bank 50 pins in top/bottom (vertical i/o) banks 50 pins in left/right side (horizontal i/o) banks 50 pins across the entire device 100 table 4?100. pll counter & clock network skews parameter worst-case skew (ps) clock skew between two external clock outputs driven by the same counter 100 clock skew between two external clock outputs driven by the different counters with the same settings 150 dual-purpose pll dedicated clock output used as i/o pin vs. regular i/o pin 270 (1) clock skew between any two outputs of the pll that drive global clock networks 150 note to table 4?100 : (1) the quartus ii software models 270 p s of delay on the pll dedicated clock output ( pll6_out[3..0]p/n and pll5_out[3..0]p/n ) pins both when used as clocks and when used as i/o pins. altera corporation 4?61 july 2005 stratix device handbook, volume 1 dc & switching characteristics the fpga device. the quartus ii softwa re calculates the i/o timing for each i/o standard with a default baseline loading as specified by the i/o standard. altera measures clock-to-output delays (t co ) at worst-case process, minimum voltage, and maximum temperature (pvt) for the 3.3-v lvttl i/o standard with 24 ma (default case ) current drive strength setting and fast slew rate setting. i/o adder de lays are measured to calculate the t co change at worst-case pvt across all i/o standards and current drive strength settings with the default loading shown in table 4?101 on page 4?62 . timing derating data for addi tional loading is taken for t co across worst-case pvt for all i/o standards and drive strength settings. these three pieces of data are used to predict the timing at the output pin. t co at pin = t outco max for 3.3-v 24 ma lvttl + i/o adder + output delay adder for loading simulation using ibis models is required to determine the delays on the pcb traces in addition to the output pin delay timing reported by the quartus ii software and the timing model in the device handbook. 1. simulate the output driver of choice into the generalized test setup using values from table 4?101 on page 4?62 . 2. record the time to vmeas. 3. simulate the output driver of ch oice into the actual pcb trace and load, using the appropriate ibis input buffer model or an equivalent capacitance value to represent the load. 4. record the time to vmeas. 5. compare the results of steps 2 and 4. the increase or decrease in delay should be added to or subt racted from the i/o standard output adder delays to yield the actual worst-case propagation delay (clock-to-input) of the pcb trace. the quartus ii software reports maxi mum timing with the conditions shown in table 4?101 on page 4?62 using the proceeding equation. figure 4?7 on page 4?62 shows the model of the ci rcuit that is represented by the quartus ii output timing. 4?62 altera corporation stratix device handbook, volume 1 july 2005 timing model figure 4?7. output delay timing reporting setup modeled by quartus ii notes to figure 4?7 : (1) output pin timing is reported at the ou tput pin of the fpga device. additional delays for loading and board trace delay need to be accounted for with ibis model simulations. (2) v ccint is 1.42-v unless otherwise specified. vccio gnd output gnd r t v tt r s c l output buffer single-ended outputs v meas gnd r up vccio r dn table 4?101. reporting methodology for maximum timi ng for single-ended output pins (part 1 of 2) notes (1) , (2) , (3) i/o standard loading and termination measurement point r up r dn r s r t v ccio (v) vtt (v) c l (pf) v meas 3.3-v lvttl ? ? 0 ? 2.950 2.95 10 1.500 2.5-v lvttl ? ? 0 ? 2.370 2.37 10 1.200 1.8-v lvttl ? ? 0 ? 1.650 1.65 10 0.880 1.5-v lvttl ? ? 0 ? 1.400 1.40 10 0.750 3.3-v lvcmos ? ? 0 ? 2.950 2.95 10 1.500 2.5-v lvcmos ? ? 0 ? 2.370 2.37 10 1.200 1.8-v lvcmos ? ? 0 ? 1.650 1.65 10 0.880 1.5-v lvcmos ? ? 0 ? 1.400 1.40 10 0.750 3.3-v gtl ? ? 0 25 2.950 1.14 30 0.740 2.5-v gtl ? ? 0 25 2.370 1.14 30 0.740 3.3-v gtl+ ? ? 0 25 2.950 1.35 30 0.880 2.5-v gtl+ ? ? 0 25 2.370 1.35 30 0.880 3.3-v sstl-3 class ii ? ? 25 25 2.950 1.25 30 1.250 altera corporation 4?63 july 2005 stratix device handbook, volume 1 dc & switching characteristics 3.3-v sstl-3 class i ? ? 25 50 2.950 1.250 30 1.250 2.5-v sstl-2 class ii ? ? 25 25 2.370 1.110 30 1.110 2.5-v sstl-2 class i ? ? 25 50 2.370 1.110 30 1.110 1.8-v sstl-18 class ii ? ? 25 25 1.650 0.760 30 0.760 1.8-v sstl-18 class i ? ? 25 50 1.650 0.760 30 0.760 1.5-v hstl class ii ? ? 0 25 1.400 0.700 20 0.680 1.5-v hstl class i ? ? 0 50 1.400 0.700 20 0.680 1.8-v hstl class ii ? ? 0 25 1.650 0.700 20 0.880 1.8-v hstl class i ? ? 0 50 1.650 0.700 20 0.880 3.3-v pci (4) ?/25 25/? 0 ? 2.950 2.950 10 0.841/1.814 3.3-v pci-x 1.0 (4) ?/25 25/? 0 ? 2.950 2.950 10 0.841/1.814 3.3-v compact pci (4) ?/25 25/? 0 ? 2.950 2.950 10 0.841/1.814 3.3-v agp 1x (4) ?/25 25/? 0 ? 2.950 2.950 10 0.841/1.814 3.3-v ctt ? ? 25 50 2.050 1.350 30 1.350 notes to table 4?101 : (1) input measurement point at internal node is 0.5 v ccint . (2) output measuring point for data is v meas . (3) input stimulus edge rate is 0 to v ccint in 0.5 ns (internal signal) from the driver preceding the io buffer. (4) the first value is for output rising edge and the second value is for output falling edge. the hyphen (-) indicates infinite resistance or disconnection. table 4?101. reporting methodology for maximum timi ng for single-ended output pins (part 2 of 2) notes (1) , (2) , (3) i/o standard loading and termination measurement point r up r dn r s r t v ccio (v) vtt (v) c l (pf) v meas 4?64 altera corporation stratix device handbook, volume 1 july 2005 timing model table 4?102 shows the reporting methodol ogy used by the quartus ii software for minimum timing information for output pins. table 4?102. reporting methodology for minimum timi ng for single-ended output pins (part 1 of 2) notes (1) , (2) , (3) i/o standard loading and termination measurement point r up r dn r s r t v ccio (v) vtt (v) c l (pf) v meas 3.3-v lvttl ? ? 0 ? 3.600 3.600 10 1.800 2.5-v lvttl ? ? 0 ? 2.630 2.630 10 1.200 1.8-v lvttl ? ? 0 ? 1.950 1.950 10 0.880 1.5-v lvttl ? ? 0 ? 1.600 1.600 10 0.750 3.3-v lvcmos ? ? 0 ? 3.600 3.600 10 1.800 2.5-v lvcmos ? ? 0 ? 2.630 2.630 10 1.200 1.8-v lvcmos ? ? 0 ? 1.950 1.950 10 0.880 1.5-v lvcmos ? ? 0 ? 1.600 1.600 10 0.750 3.3-v gtl ? ? 0 25 3.600 1.260 30 0.860 2.5-v gtl ? ? 0 25 2.630 1.260 30 0.860 3.3-v gtl+ ? ? 0 25 3.600 1.650 30 1.120 2.5-v gtl+ ? ? 0 25 2.630 1.650 30 1.120 3.3-v sstl-3 class ii ? ? 25 25 3.600 1.750 30 1.750 3.3-v sstl-3 class i ? ? 25 50 3.600 1.750 30 1.750 2.5-v sstl-2 class ii ? ? 25 25 2.630 1.390 30 1.390 2.5-v sstl-2 class i ? ? 25 50 2.630 1.390 30 1.390 1.8-v sstl-18 class ii ? ? 25 25 1.950 1.040 30 1.040 1.8-v sstl-18 class i ? ? 25 50 1.950 1.040 30 1.040 1.5-v hstl class ii ? ? 0 25 1.600 0.800 20 0.900 1.5-v hstl class i ? ? 0 50 1.600 0.800 20 0.900 1.8-v hstl class ii ? ? 0 25 1.950 0.900 20 1.000 1.8-v hstl class i ? ? 0 50 1.950 0.900 20 1.000 3.3-v pci (4) ?/25 25/? 0 ? 3.600 1.950 10 1.026/2.214 3.3-v pci-x 1.0 (4) ?/25 25/? 0 ? 3.600 1.950 10 1.026/2.214 3.3-v compact pci (4) ?/25 25/? 0 ? 3.600 3.600 10 1.026/2.214 3.3-v agp 1 (4) ?/25 25/? 0 ? 3.600 3.600 10 1.026/2.214 altera corporation 4?65 july 2005 stratix device handbook, volume 1 dc & switching characteristics figure 4?8 shows the measurement setup fo r output disable and output enable timing. the t chz stands for clock to high z time delay and is the same as t xz . the t clz stands for clock to low z (driving) time delay and is the same as t zx . figure 4?8. measurement setup for t xz and t zx 3.3-v ctt ? ? 25 50 3.600 1.650 30 1.650 notes to table 4?102 : (1) input measurement point at internal node is 0.5 v ccint . (2) output measuring point for data is v meas . when two values are given, the first is the measurement point on the rising edge and the other is for the falling edge. (3) input stimulus edge rate is 0 to v ccint in 0.5 ns (internal signal) from th e driver preceding the i/o buffer. (4) the first value is for the output rising edge and the se cond value is for the output falling edge. the hyphen (-) indicates infinite resistance or disconnection. table 4?102. reporting methodology for minimum timi ng for single-ended output pins (part 2 of 2) notes (1) , (2) , (3) i/o standard loading and termination measurement point r up r dn r s r t v ccio (v) vtt (v) c l (pf) v meas 200mv 200mv 200mv 200mv clk out out t chz t clz v t =1.5v c total =10pf r =50 4?66 altera corporation stratix device handbook, volume 1 july 2005 timing model external i/o delay parameters external i/o delay timing parameters for i/o standard input and output adders and programmable input and output delays are specified by speed grade independent of device dens ity. all of the timing parameters in this section apply to both flip-chip and wire-bond packages. tables 4?103 and 4?104 show the input adder delays associated with column and row i/o pins. if an i/o standard is selected other than 3.3-v lvttl or lvcmos, add the select ed delay to the external t insu and t insupll i/o parameters shown in tables 4?54 through 4?96 . table 4?103. stratix i/o standard colu mn pin input delay adders parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max lvcmos 0 0 0 0 ps 3.3-v lvttl 0 0 0 0 ps 2.5-v lvttl 19 19 22 26 ps 1.8-v lvttl 221 232 266 313 ps 1.5-v lvttl 352 369 425 500 ps gtl ?45 ?48 ?55 ?64 ps gtl+ ?75 ?79 ?91 ?107 ps 3.3-v pci 0 0 0 0 ps 3.3-v pci-x 1.0 0 0 0 0 ps compact pci 0 0 0 0 ps agp 1 0 0 0 0 ps agp 2 0 0 0 0 ps ctt 120 126 144 170 ps sstl-3 class i ?162 ?171 ?196 ?231 ps sstl-3 class ii ?162 ?171 ?196 ?231 ps sstl-2 class i ?202 ?213 ?244 ?287 ps sstl-2 class ii ?202 ?213 ?244 ?287 ps sstl-18 class i 78 81 94 110 ps sstl-18 class ii 78 81 94 110 ps 1.5-v hstl class i ?76 ?80 ?92 ?108 ps 1.5-v hstl class ii ?76 ?80 ?92 ?108 ps 1.8-v hstl class i ?52 ?55 ?63 ?74 ps 1.8-v hstl class ii ?52 ?55 ?63 ?74 ps altera corporation 4?67 july 2005 stratix device handbook, volume 1 dc & switching characteristics table 4?104. stratix i/o standard row pin input delay adders parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max lvcmos 0 0 0 0 ps 3.3-v lvttl 0 0 0 0 ps 2.5-v lvttl 21 22 25 29 ps 1.8-v lvttl 181 190 218 257 ps 1.5-v lvttl 300 315 362 426 ps gtl+ ?152 ?160 ?184 ?216 ps ctt ?168 ?177 ?203 ?239 ps sstl-3 class i ?193 ?203 ?234 ?275 ps sstl-3 class ii ?193 ?203 ?234 ?275 ps sstl-2 class i ?262 ?276 ?317 ?373 ps sstl-2 class ii ?262 ?276 ?317 ?373 ps sstl-18 class i ?105 ?111 ?127 ?150 ps sstl-18 class ii 0 0 0 0 ps 1.5-v hstl class i ?151 ?159 ?183 ?215 ps 1.8-v hstl class i ?126 ?133 ?153 ?179 ps lvds ?149 ?157 ?180 ?212 ps lvpecl ?149 ?157 ?180 ?212 ps 3.3-v pcml ?65 ?69 ?79 ?93 ps hypertransport 77 ?81 ?93 ?110 ps 4?68 altera corporation stratix device handbook, volume 1 july 2005 timing model tables 4?105 through 4?108 show the output adder delays associated with column and row i/o pins for both fast and slow slew rates. if an i/o standard is selected other than 3. 3-v lvttl 4ma or lvcmos 2 ma with a fast slew rate, add the selected delay to the external t outco , t outcopll , t xz , t zx , t xzpll , and t zxpll i/o parameters shown in table 4?55 on page 4?36 through table 4?96 on page 4?56 . table 4?105. stratix i/o standar d output delay adders for fast slew rate on column pins (part 1 of 2) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max lvcmos 2 ma 1,895 1,990 1,990 1,990 ps 4 ma 956 1,004 1,004 1,004 ps 8 ma 189 198 198 198 ps 12 ma 0 0 0 0ps 24 ma ?157 ?165 ?165 ?165 ps 3.3-v lvttl 4 ma 1,895 1,990 1,990 1,990 ps 8 ma 1,347 1,414 1,414 1,414 ps 12 ma 636 668 668 668 ps 16 ma 561 589 589 589 ps 24 ma 0 0 0 0ps 2.5-v lvttl 2 ma 2,517 2,643 2,643 2,643 ps 8 ma 834 875 875 875 ps 12 ma 504 529 529 529 ps 16 ma 194 203 203 203 ps 1.8-v lvttl 2 ma 1,304 1,369 1,369 1,369 ps 8 ma 960 1,008 1,008 1,008 ps 12 ma 960 1,008 1,008 1,008 ps 1.5-v lvttl 2 ma 6,680 7,014 7,014 7,014 ps 4 ma 3,275 3,439 3,439 3,439 ps 8 ma 1,589 1,668 1,668 1,668 ps gtl 16 17 17 17 ps gtl+ 9 9 9 9ps 3.3-v pci 50 52 52 52 ps 3.3-v pci-x 1.0 50 52 52 52 ps compact pci 50 52 52 52 ps agp 1 50 52 52 52 ps agp 2 1,895 1,990 1,990 1,990 ps altera corporation 4?69 july 2005 stratix device handbook, volume 1 dc & switching characteristics ctt 973 1,021 1,021 1,021 ps sstl-3 class i 719 755 755 755 ps sstl-3 class ii 146 153 153 153 ps sstl-2 class i 678 712 712 712 ps sstl-2 class ii 223 234 234 234 ps sstl-18 class i 1,032 1,083 1,083 1,083 ps sstl-18 class ii 447 469 469 469 ps 1.5-v hstl class i 660 693 693 693 ps 1.5-v hstl class ii 537 564 564 564 ps 1.8-v hstl class i 304 319 319 319 ps 1.8-v hstl class ii 231 242 242 242 ps table 4?106. stratix i/o standar d output delay adders for fast slew rate on row pins (part 1 of 2) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max lvcmos 2 ma 1,518 1,594 1,594 1,594 ps 4 ma 746 783 783 783 ps 8 ma 96 100 100 100 ps 12 ma 0 0 0 0ps 3.3-v lvttl 4 ma 1,518 1,594 1,594 1,594 ps 8 ma 1,038 1,090 1,090 1,090 ps 12 ma 521 547 547 547 ps 16 ma 414 434 434 434 ps 24 ma 0 0 0 0ps 2.5-v lvttl 2 ma 2,032 2,133 2,133 2,133 ps 8 ma 699 734 734 734 ps 12 ma 374 392 392 392 ps 16 ma 165 173 173 173 ps 1.8-v lvttl 2 ma 3,714 3,899 3,899 3,899 ps 8 ma 1,055 1,107 1,107 1,107 ps 12 ma 830 871 871 871 ps table 4?105. stratix i/o standar d output delay adders for fast slew rate on column pins (part 2 of 2) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max 4?70 altera corporation stratix device handbook, volume 1 july 2005 timing model 1.5-v lvttl 2 ma 5,460 5,733 5,733 5,733 ps 4 ma 2,690 2,824 2,824 2,824 ps 8 ma 1,398 1,468 1,468 1,468 ps gtl+ 6 6 6 6ps ctt 845 887 887 887 ps sstl-3 class i 638 670 670 670 ps sstl-3 class ii 144 151 151 151 ps sstl-2 class i 604 634 634 634 ps sstl-2 class ii 211 221 221 221 ps sstl-18 class i 955 1,002 1,002 1,002 ps 1.5-v hstl class i 733 769 769 769 ps 1.8-v hstl class i 372 390 390 390 ps lvds ?196 ?206 ?206 ?206 ps lvpecl ?148 ?156 ?156 ?156 ps pcml ?147 ?155 ?155 ?155 ps hypertransport technology ?93 ?98 ?98 ?98 ps note to table 4?103 through 4?106 : (1) these parameters are only available on row i/o pins. table 4?107. stratix i/o standard output delay adders fo r slow slew rate on column pins (part 1 of 2) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max lvcmos 2 ma 1,822 1,913 1,913 1,913 ps 4 ma 684 718 718 718 ps 8 ma 233 245 245 245 ps 12 ma1111ps 24 ma ?608 ?638 ?638 ?638 ps table 4?106. stratix i/o standar d output delay adders for fast slew rate on row pins (part 2 of 2) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max altera corporation 4?71 july 2005 stratix device handbook, volume 1 dc & switching characteristics 3.3-v lvttl 4 ma 1,822 1,913 1,913 1,913 ps 8 ma 1,586 1,665 1,665 1,665 ps 12 ma 686 720 720 720 ps 16 ma 630 662 662 662 ps 24 ma0000ps 2.5-v lvttl 2 ma 2,925 3,071 3,071 3,071 ps 8 ma 1,496 1,571 1,571 1,571 ps 12 ma 937 984 984 984 ps 16 ma 1,003 1,053 1,053 1,053 ps 1.8-v lvttl 2 ma 7,101 7,456 7,456 7,456 ps 8 ma 3,620 3,801 3,801 3,801 ps 12 ma 3,109 3,265 3,265 3,265 ps 1.5-v lvttl 2 ma 10,941 11,488 11,488 11,488 ps 4 ma 7,431 7,803 7,803 7,803 ps 8 ma 5,990 6,290 6,290 6,290 ps gtl ?959 ?1,007 ?1,007 ?1,007 ps gtl+ ?438 ?460 ?460 ?460 ps 3.3-v pci 660 693 693 693 ps 3.3-v pci-x 1.0 660 693 693 693 ps compact pci 660 693 693 693 ps agp 1 660 693 693 693 ps agp 2 288 303 303 303 ps ctt 631 663 663 663 ps sstl-3 class i 301 316 316 316 ps sstl-3 class ii ?359 ?377 ?377 ?377 ps sstl-2 class i 523 549 549 549 ps sstl-2 class ii ?49 ?51 ?51 ?51 ps sstl-18 class i 2,315 2,431 2,431 2,431 ps sstl-18 class ii 723 759 759 759 ps 1.5-v hstl class i 1,687 1,771 1,771 1,771 ps 1.5-v hstl class ii 1,095 1,150 1,150 1,150 ps 1.8-v hstl class i 599 629 678 744 ps 1.8-v hstl class ii 87 102 102 102 ps table 4?107. stratix i/o standard output delay adders fo r slow slew rate on column pins (part 2 of 2) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max 4?72 altera corporation stratix device handbook, volume 1 july 2005 timing model table 4?108. stratix i/o standard output delay adders for slow slew rate on row pins i/o standard -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max lvcmos 2 ma 1,571 1,650 1,650 1,650 ps 4 ma 594 624 624 624 ps 8 ma 208 218 218 218 ps 12 ma 0 0 0 0ps 3.3-v lvttl 4 ma 1,571 1,650 1,650 1,650 ps 8 ma 1,393 1,463 1,463 1,463 ps 12 ma 596 626 626 626 ps 16 ma 562 590 590 590 ps 2.5-v lvttl 2 ma 2,562 2,690 2,690 2,690 ps 8 ma 1,343 1,410 1,410 1,410 ps 12 ma 864 907 907 907 ps 16 ma 945 992 992 992 ps 1.8-v lvttl 2 ma 6,306 6,621 6,621 6,621 ps 8 ma 3,369 3,538 3,538 3,538 ps 12 ma 2,932 3,079 3,079 3,079 ps 1.5-v lvttl 2 ma 9,759 10,247 10,247 10,247 ps 4 ma 6,830 7,172 7,172 7,172 ps 8 ma 5,699 5,984 5,984 5,984 ps gtl+ ?333 ?350 ?350 ?350 ps ctt 591 621 621 621 ps sstl-3 class i 267 280 280 280 ps sstl-3 class ii ?346 ?363 ?363 ?363 ps sstl-2 class i 481 505 505 505 ps sstl-2 class ii ?58 ?61 ?61 ?61 ps sstl-18 class i 2,207 2,317 2,317 2,317 ps 1.5-v hstl class i 1,966 2,064 2,064? 2,064 ps 1.8-v hstl class i 1,208 1,268 1,460 1,720 ps altera corporation 4?73 july 2005 stratix device handbook, volume 1 dc & switching characteristics tables 4?109 and 4?110 show the adder delays for the column and row ioe programmable delays. these delays are controlled with the quartus ii software logic options listed in the parameter column. table 4?109. stratix ioe programmable delays on column pins note (1) parameter setting -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max decrease input delay to internal cells off 3,970 4,367 5,022 5,908 ps small 3,390 3,729 4,288 5,045 ps medium 2,810 3,091 3,554 4,181 ps large 224 235 270 318 ps on 224 235 270 318 ps decrease input delay to input register off 3,900 4,290 4,933 5,804 ps on 0000ps decrease input delay to output register off 1,240 1,364 1,568 1,845 ps on 0000ps increase delay to output pin off 0000ps on 397 417 417 417 ps increase delay to output enable pin off 0000ps on 338 372 427 503 ps increase output clock enable delay off 0000ps small 540 594 683 804 ps large 1,016 1,118 1,285 1,512 ps on 1,016 1,118 1,285 1,512 ps increase input clock enable delay off 0000ps small 540 594 683 804 ps large 1,016 1,118 1,285 1,512 ps on 1,016 1,118 1,285 1,512 ps increase output enable clock enable delay off 0000ps small 540 594 683 804 ps large 1,016 1,118 1,285 1,512 ps on 1,016 1,118 1,285 1,512 ps increase t zx delay to output pin off 0000ps on 2,199 2,309 2,309 2,309 ps 4?74 altera corporation stratix device handbook, volume 1 july 2005 timing model table 4?110. stratix ioe programmable delays on row pins note (1) parameter setting -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max decrease input delay to internal cells off 3,970 4,367 5,022 5,908 ps small 3,390 3,729 4,288 5,045 ps medium 2,810 3,091 3,554 4,181 ps large 173 181 208 245 ps on 173 181 208 245 ps decrease input delay to input register off 3,900 4,290 4,933 5,804 ps on 0000ps decrease input delay to output register off 1,240 1,364 1,568 1,845 ps on 0000ps increase delay to output pin off 0000ps on 397 417 417 417 ps increase delay to output enable pin off 0000ps on 348 383 441 518 ps increase output clock enable delay off 0000ps small 180 198 227 267 ps large 260 286 328 386 ps on 260 286 328 386 ps increase input clock enable delay off 0000ps small 180 198 227 267 ps large 260 286 328 386 ps on 260 286 328 386 ps increase output enable clock enable delay off 0000ps small 540 594 683 804 ps large 1,016 1,118 1,285 1,512 ps on 1,016 1,118 1,285 1,512 ps increase t zx delay to output pin off 0000ps on 1,993 2,092 2,092 2,092 ps note to table 4?109 and ta b l e 4 ? 11 0 : (1) the delay chain delays vary for different device densitie s. these timing values only apply to ep1s30 and ep1s40 devices. reference the timing information report ed by the quartus ii software for other devices. altera corporation 4?75 july 2005 stratix device handbook, volume 1 dc & switching characteristics the scaling factors for col umn output pin timing in tables 4?111 to 4?113 are shown in units of time per pf un it of capacitance (ps/pf). add this delay to the t co or combinatorial timing path for output or bidirectional pins in addition to the i /o adder delays shown in tables 4?103 through 4?108 and the ioe programmable delays in tables 4?109 and 4?110 . table 4?111. output delay adder for loadi ng on lvttl/lvcmos output buffers note (1) conditions output pin adder delay (ps/pf) parameter value 3.3-v lvttl 2.5-v lvttl 1.8-v lvttl 1.5-v lvttl lvcmos drive strength 24ma 15 ? ? - 8 16ma 25 18 ? ? ? 12ma 30 25 25 ? 15 8ma 50 35 40 35 20 4ma 60 ? ? 80 30 2ma ? 75 120 160 60 note to ta b l e 4 ? 111 : (1) the timing information in this table is preliminary. table 4?112. output delay adder for loading on sstl/hstl output buffers note (1) conditions output pin adder delay (ps/pf) sstl-3 sstl-2 sstl-1.8 1.5-v hstl class i class ii 25 25 25 25 25 20 25 20 note to table 4?112 : (1) the timing information in this table is preliminary. table 4?113. output delay adder for loading on gtl+/gtl/ctt/pci output buffers note (1) conditions output pin adder delay (ps/pf) parameter value gtl+ gtl ctt pci agp vccio voltage level 3.3v 18 18 25 20 20 2.5v 15 18 - - - note to table 4?113 : (1) the timing information in this table is preliminary. 4?76 altera corporation stratix device handbook, volume 1 july 2005 timing model maximum input & output clock rates tables 4?114 through 4?119 show the maximum input clock rate for column and row pins in stratix devices. table 4?114. stratix maximum input clock rate for clk[7..4] & clk[15..12] pins in flip-chip packages (part 1 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit lvttl 422 422 390 390 mhz 2.5 v 422 422 390 390 mhz 1.8 v 422 422 390 390 mhz 1.5 v 422 422 390 390 mhz lvcmos 422 422 390 390 mhz gtl 300 250 200 200 mhz gtl+ 300 250 200 200 mhz sstl-3 class i 400 350 300 300 mhz sstl-3 class ii 400 350 300 300 mhz sstl-2 class i 400 350 300 300 mhz sstl-2 class ii 400 350 300 300 mhz sstl-18 class i 400 350 300 300 mhz sstl-18 class ii 400 350 300 300 mhz 1.5-v hstl class i 400 350 300 300 mhz 1.5-v hstl class ii 400 350 300 300 mhz 1.8-v hstl class i 400 350 300 300 mhz 1.8-v hstl class ii 400 350 300 300 mhz 3.3-v pci 422 422 390 390 mhz 3.3-v pci-x 1.0 422 422 390 390 mhz compact pci 422 422 390 390 mhz agp 1 422 422 390 390 mhz agp 2 422 422 390 390 mhz ctt 300 250 200 200 mhz differential 1.5-v hstl c1 400 350 300 300 mhz lvpecl (1) 645 645 622 622 mhz pcml (1) 300 275 275 275 mhz altera corporation 4?77 july 2005 stratix device handbook, volume 1 dc & switching characteristics lv d s (1) 645 645 622 622 mhz hypertransport technology (1) 500 500 450 450 mhz table 4?115. stratix maximum input clock ra te for clk[0, 2, 9, 11] pins & fpll[10..7]clk pins in flip-chip packages i/o standard -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit lvttl 422 422 390 390 mhz 2.5 v 422 422 390 390 mhz 1.8 v 422 422 390 390 mhz 1.5 v 422 422 390 390 mhz lvcmos 422 422 390 390 mhz gtl+ 300 250 200 200 mhz sstl-3 class i 400 350 300 300 mhz sstl-3 class ii 400 350 300 300 mhz sstl-2 class i 400 350 300 300 mhz sstl-2 class ii 400 350 300 300 mhz sstl-18 class i 400 350 300 300 mhz sstl-18 class ii 400 350 300 300 mhz 1.5-v hstl class i 400 350 300 300 mhz 1.8-v hstl class i 400 350 300 300 mhz ctt 300 250 200 200 mhz differential 1.5-v hstl c1 400 350 300 300 mhz lvpecl (1) 717 717 640 640 mhz pcml (1) 400 375 350 350 mhz lv d s (1) 717 717 640 640 mhz hypertransport technology (1) 717 717 640 640 mhz table 4?114. stratix maximum input clock rate for clk[7..4] & clk[15..12] pins in flip-chip packages (part 2 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit 4?78 altera corporation stratix device handbook, volume 1 july 2005 timing model table 4?116. stratix maximum input clock rate for clk[1, 3, 8, 10] pins in flip-chip packages i/o standard -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit lvttl 422 422 390 390 mhz 2.5 v 422 422 390 390 mhz 1.8 v 422 422 390 390 mhz 1.5 v 422 422 390 390 mhz lvcmos 422 422 390 390 mhz gtl+ 300 250 200 200 mhz sstl-3 class i 400 350 300 300 mhz sstl-3 class ii 400 350 300 300 mhz sstl-2 class i 400 350 300 300 mhz sstl-2 class ii 400 350 300 300 mhz sstl-18 class i 400 350 300 300 mhz sstl-18 class ii 400 350 300 300 mhz 1.5-v hstl class i 400 350 300 300 mhz 1.8-v hstl class i 400 350 300 300 mhz ctt 300 250 200 200 mhz differential 1.5-v hstl c1 400 350 300 300 mhz lvpecl (1) 645 645 640 640 mhz pcml (1) 300 275 275 275 mhz lv d s (1) 645 645 640 640 mhz hypertransport technology (1) 500 500 450 450 mhz table 4?117. stratix maximum input clock rate for clk[7..4] & clk[15..12] pins in wire-bond packages (part 1 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 422 390 390 mhz 2.5 v 422 390 390 mhz 1.8 v 422 390 390 mhz 1.5 v 422 390 390 mhz lvcmos 422 390 390 mhz gtl 250 200 200 mhz altera corporation 4?79 july 2005 stratix device handbook, volume 1 dc & switching characteristics gtl+ 250 200 200 mhz sstl-3 class i 300 250 250 mhz sstl-3 class ii 300 250 250 mhz sstl-2 class i 300 250 250 mhz sstl-2 class ii 300 250 250 mhz sstl-18 class i 300 250 250 mhz sstl-18 class ii 300 250 250 mhz 1.5-v hstl class i 300 180 180 mhz 1.5-v hstl class ii 300 180 180 mhz 1.8-v hstl class i 300 180 180 mhz 1.8-v hstl class ii 300 180 180 mhz 3.3-v pci 422 390 390 mhz 3.3-v pci-x 1.0 422 390 390 mhz compact pci 422 390 390 mhz agp 1 422 390 390 mhz agp 2 422 390 390 mhz ctt 250 180 180 mhz differential 1.5-v hstl c1 300 180 180 mhz lvpecl (1) 422 400 400 mhz pcml (1) 215 200 200 mhz lv d s (1) 422 400 400 mhz hypertransport technology (1) 422 400 400 mhz table 4?118. stratix maximum input clock ra te for clk[0, 2, 9, 11] pins & fpll[10..7]clk pins in wire-bond packages (part 1 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 422 390 390 mhz 2.5 v 422 390 390 mhz 1.8 v 422 390 390 mhz 1.5 v 422 390 390 mhz table 4?117. stratix maximum input clock rate for clk[7..4] & clk[15..12] pins in wire-bond packages (part 2 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit 4?80 altera corporation stratix device handbook, volume 1 july 2005 timing model lvcmos 422 390 390 mhz gtl+ 250 200 200 mhz sstl-3 class i 350 300 300 mhz sstl-3 class ii 350 300 300 mhz sstl-2 class i 350 300 300 mhz sstl-2 class ii 350 300 300 mhz sstl-18 class i 350 300 300 mhz sstl-18 class ii 350 300 300 mhz 1.5-v hstl class i 350 300 300 mhz 1.8-v hstl class i 350 300 300 mhz ctt 250 200 200 mhz differential 1.5-v hstl c1 350 300 300 mhz lvpecl (1) 717 640 640 mhz pcml (1) 375 350 350 mhz lv d s (1) 717 640 640 mhz hypertransport technology (1) 717 640 640 mhz table 4?119. stratix maximum input clock ra te for clk[1, 3, 8, 10] pins in wire-bond packages (part 1 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 422 390 390 mhz 2.5 v 422 390 390 mhz 1.8 v 422 390 390 mhz 1.5 v 422 390 390 mhz lvcmos 422 390 390 mhz gtl+ 250 200 200 mhz sstl-3 class i 350 300 300 mhz sstl-3 class ii 350 300 300 mhz sstl-2 class i 350 300 300 mhz sstl-2 class ii 350 300 300 mhz table 4?118. stratix maximum input clock ra te for clk[0, 2, 9, 11] pins & fpll[10..7]clk pins in wire-bond packages (part 2 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit altera corporation 4?81 july 2005 stratix device handbook, volume 1 dc & switching characteristics tables 4?120 through 4?123 show the maximum output clock rate for column and row pins in stratix devices. sstl-18 class i 350 300 300 mhz sstl-18 class ii 350 300 300 mhz 1.5-v hstl class i 350 300 300 mhz 1.8-v hstl class i 350 300 300 mhz ctt 250 200 200 mhz differential 1.5-v hstl c1 350 300 300 mhz lvpecl (1) 645 622 622 mhz pcml (1) 275 275 275 mhz lv d s (1) 645 622 622 mhz hypertransport technology (1) 500 450 450 mhz note to ta b l e s 4 ? 11 4 through 4?119 : (1) these parameters are only available on row i/o pins. table 4?120. stratix maximum output clock rate for pll[5, 6, 11, 12] pins in flip-chip packages (part 1 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit lvttl 350 300 250 250 mhz 2.5 v 350 300 300 300 mhz 1.8 v 250 250 250 250 mhz 1.5 v 225 200 200 200 mhz lvcmos 350 300 250 250 mhz gtl 200 167 125 125 mhz gtl+ 200 167 125 125 mhz sstl-3 class i 200 167 167 133 mhz sstl-3 class ii 200 167 167 133 mhz sstl-2 class i (3) 200 200 167 167 mhz sstl-2 class i (4) 200 200 167 167 mhz sstl-2 class i (5) 150 134 134 134 mhz table 4?119. stratix maximum input clock ra te for clk[1, 3, 8, 10] pins in wire-bond packages (part 2 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit 4?82 altera corporation stratix device handbook, volume 1 july 2005 timing model sstl-2 class ii (3) 200 200 167 167 mhz sstl-2 class ii (4) 200 200 167 167 mhz sstl-2 class ii (5) 150 134 134 134 mhz sstl-18 class i 150 133 133 133 mhz sstl-18 class ii 150 133 133 133 mhz 1.5-v hstl class i 250 225 200 200 mhz 1.5-v hstl class ii 225 200 200 200 mhz 1.8-v hstl class i 250 225 200 200 mhz 1.8-v hstl class ii 225 200 200 200 mhz 3.3-v pci 350 300 250 250 mhz 3.3-v pci-x 1.0 350 300 250 250 mhz compact pci 350 300 250 250 mhz agp 1 350 300 250 250 mhz agp 2 350 300 250 250 mhz ctt 200 200 200 200 mhz differential 1.5-v hstl c1 225 200 200 200 mhz differential 1.8-v hstl class i 250 225 200 200 mhz differential 1.8-v hstl class ii 225 200 200 200 mhz differential sstl-2 (6) 200 200 167 167 mhz lvpecl (2) 500 500 500 500 mhz pcml (2) 350 350 350 350 mhz lv d s (2) 500 500 500 500 mhz hypertransport technology (2) 350 350 350 350 mhz table 4?120. stratix maximum output clock rate for pll[5, 6, 11, 12] pins in flip-chip packages (part 2 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit altera corporation 4?83 july 2005 stratix device handbook, volume 1 dc & switching characteristics table 4?121. stratix maximum output cloc k rate (using i/o pins) for pll[1, 2, 3, 4] pins in flip-chip packages i/o standard -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit lvttl 400 350 300 300 mhz 2.5 v 400 350 300 300 mhz 1.8 v 400 350 300 300 mhz 1.5 v 350 300 300 300 mhz lvcmos 400 350 300 300 mhz gtl 200 167 125 125 mhz gtl+ 200 167 125 125 mhz sstl-3 class i 167 150 133 133 mhz sstl-3 class ii 167 150 133 133 mhz sstl-2 class i 150 133 133 133 mhz sstl-2 class ii 150 133 133 133 mhz sstl-18 class i 150 133 133 133 mhz sstl-18 class ii 150 133 133 133 mhz 1.5-v hstl class i 250 225 200 200 mhz 1.5-v hstl class ii 225 225 200 200 mhz 1.8-v hstl class i 250 225 200 200 mhz 1.8-v hstl class ii 225 225 200 200 mhz 3.3-v pci 250 225 200 200 mhz 3.3-v pci-x 1.0 225 225 200 200 mhz compact pci 400 350 300 300 mhz agp 1 400 350 300 300 mhz agp 2 400 350 300 300 mhz ctt 300 250 200 200 mhz lvpecl (2) 717 717 500 500 mhz pcml (2) 420 420 420 420 mhz lv d s (2) 717 717 500 500 mhz hypertransport technology (2) 420 420 420 420 mhz 4?84 altera corporation stratix device handbook, volume 1 july 2005 timing model table 4?122. stratix maximum output clock rate for pll[5, 6, 11, 12] pins in wire-bond packages (part 1 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 175 150 150 mhz 2.5 v 175 150 150 mhz 1.8 v 175 150 150 mhz 1.5 v 175 150 150 mhz lvcmos 175 150 150 mhz gtl 125 100 100 mhz gtl+ 125 100 100 mhz sstl-3 class i 110 90 90 mhz sstl-3 class ii 133 125 125 mhz sstl-2 class i 166 133 133 mhz sstl-2 class ii 133 100 100 mhz sstl-18 class i 110 100 100 mhz sstl-18 class ii 110 100 100 mhz 1.5-v hstl class i 167 167 167 mhz 1.5-v hstl class ii 167 133 133 mhz 1.8-v hstl class i 167 167 167 mhz 1.8-v hstl class ii 167 133 133 mhz 3.3-v pci 167 167 167 mhz 3.3-v pci-x 1.0 167 133 133 mhz compact pci 175 150 150 mhz agp 1 175 150 150 mhz agp 2 175 150 150 mhz ctt 125 100 100 mhz differential 1.5-v hstl c1 167 133 133 mhz differential 1.8-v hstl class i 167 167 167 mhz differential 1.8-v hstl class ii 167 133 133 mhz differential sstl-2 (1) 110 100 100 mhz lvpecl (2) 311 275 275 mhz pcml (2) 250 200 200 mhz altera corporation 4?85 july 2005 stratix device handbook, volume 1 dc & switching characteristics lv d s (2) 311 275 275 mhz hypertransport technology (2) 311 275 275 mhz table 4?123. stratix maximum output cloc k rate (using i/o pins) for pll[1, 2, 3, 4] pins in wire-bond packages (part 1 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 200 175 175 mhz 2.5 v 200 175 175 mhz 1.8 v 200 175 175 mhz 1.5 v 200 175 175 mhz lvcmos 200 175 175 mhz gtl 125 100 100 mhz gtl+ 125 100 100 mhz sstl-3 class i 110 90 90 mhz sstl-3 class ii 150 133 133 mhz sstl-2 class i 90 80 80 mhz sstl-2 class ii 110 100 100 mhz sstl-18 class i 110 100 100 mhz sstl-18 class ii 110 100 100 mhz 1.5-v hstl class i 225 200 200 mhz 1.5-v hstl class ii 200 167 167 mhz 1.8-v hstl class i 225 200 200 mhz 1.8-v hstl class ii 200 167 167 mhz 3.3-v pci 200 175 175 mhz 3.3-v pci-x 1.0 200 175 175 mhz compact pci 200 175 175 mhz agp 1 200 175 175 mhz agp 2 200 175 175 mhz ctt 125 100 100 mhz lvpecl (2) 311 270 270 mhz pcml (2) 400 311 311 mhz table 4?122. stratix maximum output clock rate for pll[5, 6, 11, 12] pins in wire-bond packages (part 2 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit 4?86 altera corporation stratix device handbook, volume 1 july 2005 timing model lv d s (2) 400 311 311 mhz hypertransport technology (2) 420 400 400 mhz notes to tables 4?120 through 4?123 : (1) differential sstl-2 outputs are on ly available on column clock pins. (2) these parameters are only available on row i/o pins. (3) sstl-2 in maximum drive strength condition. see table 4?101 on page 4?62 for more information on exact loading conditions for each i/o standard. (4) sstl-2 in minimum drive strength with 10pf output load condition. (5) sstl-2 in minimum drive strength with > 10pf output load condition. (6) differential sstl-2 outputs are on ly supported on column clock pins. table 4?123. stratix maximum output cloc k rate (using i/o pins) for pll[1, 2, 3, 4] pins in wire-bond packages (part 2 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit altera corporation 4?87 july 2005 stratix device handbook, volume 1 dc & switching characteristics high-speed i/o specification table 4?124 provides high-spe ed timing specific ations definitions. table 4?124. high-speed timing s pecifications & terminology high-speed timing spec ification terminology t c high-speed receiver/transmitter input and output clock period. f hsclk high-speed receiver/transmitter input and output clock frequency. t rise low-to-high transmission time. t fall high-to-low transmission time. timing unit interval (tui) the timing budget allowed for skew, propagation delays, and data sampling window. (tui = 1/(receiver input clock frequency multiplication factor) = t c / w ). f hsdr maximum lvds data transfer rate (f hsdr = 1/tui). channel-to-channel skew (tccs) the timing differenc e between the fastest and slowest output edges, including t co variation and clock skew. the clock is included in the tccs measurement. sampling window (sw) the period of time during which the data must be valid to be captured correctly. the setup and hold time s determine the ideal strobe position within the sampling window. sw = t sw (max) ? t sw (min). input jitter (peak-to-peak) peak-to-p eak input jitter on high-speed plls. output jitter (peak-to-peak) peak-to-p eak output jitter on high-speed plls. t duty duty cycle on high-speed transmitter output clock. t lock lock time for high-speed transmitter and receiver plls. j deserialization factor (width of internal data bus). w pll multiplication factor. 4?88 altera corporation stratix device handbook, volume 1 july 2005 high-speed i/o specification tables 4?125 and 4?126 show the high-speed i/o timing for stratix devices. table 4?125. high-speed i/o spec ifications for flip-chip packages (part 1 of 4) notes (1) , (2) symbol conditions -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max min typ max f hsclk (clock frequency) (lvds, lvpecl, hypertransport technology) f hsclk = f hsdr / w w = 4 to 30 (serdes used) 10 210 10 210 10 156 10 115.5 mhz w = 2 (serdes bypass) 50 231 50 231 50 231 50 231 mhz w = 2 (serdes used) 150 420 150 420 150 312 150 231 mhz w = 1 (serdes bypass) 100 462 100 462 100 462 100 462 mhz w = 1 (serdes used) 300 717 300 717 300 624 300 462 mhz f hsdr device operation (lvds, lvpecl, hypertransport technology) j = 10 300 840 300 840 300 640 300 462 mbps j = 8 300 840 300 840 300 640 300 462 mbps j = 7 300 840 300 840 300 640 300 462 mbps j = 4 300 840 300 840 300 640 300 462 mbps j = 2 100 462 100 462 100 640 100 462 mbps j = 1 (lvds and lvpecl only) 100 462 100 462 100 640 100 462 mbps altera corporation 4?89 july 2005 stratix device handbook, volume 1 high-speed i/o specification f hsclk (clock frequency) (pcml) f hsclk = f hsdr / w w = 4 to 30 (serdes used) 10 100 10 100 10 77.75 10 77.75 mhz w = 2 (serdes bypass) 50 200 50 200 50 150 50 150 mhz w = 2 (serdes used) 150 200 150 200 150 155.5 150 155.5 mhz w = 1 (serdes bypass) 100 250 100 250 100 200 100 200 mhz w = 1 (serdes used) 300 400 300 400 300 311 300 311 mhz f hsdr device operation (pcml) j = 10 300 400 300 400 300 311 300 311 mbps j = 8 300 400 300 400 300 311 300 311 mbps j = 7 300 400 300 400 300 311 300 311 mbps j = 4 300 400 300 400 300 311 300 311 mbps j = 2 100 400 100 400 100 300 100 300 mbps j = 1 100 250 100 250 100 200 100 200 mbps tccs all 200 200 300 300 ps table 4?125. high-speed i/o spec ifications for flip-chip packages (part 2 of 4) notes (1) , (2) symbol conditions -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max min typ max 4?90 altera corporation stratix device handbook, volume 1 july 2005 high-speed i/o specification sw pcml ( j = 4, 7, 8, 10) 750 750 800 800 ps pcml ( j = 2) 900 900 1,200 1,200 ps pcml ( j = 1) 1,500 1,500 1,700 1,700 ps lvds and lvpecl ( j =1) 500 500 550 550 ps lv d s, lvpecl, hypertransport technology ( j = 2 through 10) 440 440 500 500 ps input jitter tolerance (peak-to-peak) all 250 250 250 250 ps output jitter (peak-to-peak) all 160 160 200 200 ps output t rise lvds 80 110 120 80 110 120 80 110 120 80 110 120 ps hypertransport technology 110 170 200 110 170 200 120 170 200 120 170 200 ps lvpecl 90 130 150 90 130 150 100 135 150 100 135 150 ps pcml 80 110 135 80 110 135 80 110 135 80 110 135 ps output t fall lvds 80 110 120 80 110 120 80 110 120 80 110 120 ps hypertransport technology 110 170 200 110 170 200 110 170 200 110 170 200 ps lvpecl 90 130 160 90 130 160 100 135 160 100 135 160 ps pcml 105 140 175 105 140 175 110 145 175 110 145 175 ps table 4?125. high-speed i/o spec ifications for flip-chip packages (part 3 of 4) notes (1) , (2) symbol conditions -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max min typ max altera corporation 4?91 july 2005 stratix device handbook, volume 1 high-speed i/o specification t duty lv d s ( j =2 through 10) 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 % lv d s ( j =1) and lvpecl, pcml, hypertransport technology 45 50 55 45 50 55 45 50 55 45 50 55 % t lock all 100 100 100 100 s notes to table 4?125 : (1) when j = 4, 7, 8, and 10, the serdes block is used. (2) when j = 2 or j = 1, the serdes is bypassed. table 4?125. high-speed i/o spec ifications for flip-chip packages (part 4 of 4) notes (1) , (2) symbol conditions -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max min typ max 4?92 altera corporation stratix device handbook, volume 1 july 2005 high-speed i/o specification table 4?126. high-speed i/o s pecifications for wire-b ond packages (part 1 of 2) symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max f hsclk (clock frequency) (lvds,lvpecl, hypertransport technology) f hsclk = f hsdr / w w = 4 to 30 (serdes used) 10 156 10 115.5 10 115.5 mhz w = 2 (serdes bypass) 50 231 50 231 50 231 mhz w = 2 (serdes used) 150 312 150 231 150 231 mhz w = 1 (serdes bypass) 100 311 100 270 100 270 mhz w = 1 (serdes used) 300 624 300 462 300 462 mhz f hsdr device operation, (lvds,lvpecl, hypertransport technology) j = 10 300 624 300 462 300 462 mbps j = 8 300 624 300 462 300 462 mbps j = 7 300 624 300 462 300 462 mbps j = 4 300 624 300 462 300 462 mbps j = 2 100 462 100 462 100 462 mbps j = 1 (lvds and lvpecl only) 100 311 100 270 100 270 mbps f hsclk (clock frequency) (pcml) f hsclk = f hsdr / w w = 4 to 30 (serdes used) 10 77.75 mhz w = 2 (serdes bypass) 50 150 50 77.5 50 77.5 mhz w = 2 (serdes used) 150 155.5 mhz w = 1 (serdes bypass) 100 200 100 155 100 155 mhz w = 1 (serdes used) 300 311 mhz device operation, f hsdr (pcml) j = 10 300 311 mbps j = 8 300 311 mbps j = 7 300 311 mbps j = 4 300 311 mbps j = 2 100 300 100 155 100 155 mbps j = 1 100 200 100 155 100 155 mbps tccs all 400 400 400 ps altera corporation 4?93 july 2005 stratix device handbook, volume 1 high-speed i/o specification sw pcml (j = 4, 7, 8, 10) only 800 800 800 ps pcml (j = 2) only 1,200 1,200 1,200 ps pcml (j = 1) only 1,700 1,700 1,700 ps lvds and lvpecl (j = 1) only 550 550 550 ps lvds, lvpecl, hypertransport technology (j = 2 through 10) only 500 500 500 ps input jitter tolerance (peak-to-peak) all 250 250 250 ps output jitter (peak-to- peak) all 200 200 200 ps output t rise lvds 80 110 120 80 110 120 80 110 120 ps hypertransport technology 120 170 200 120 170 200 120 170 200 ps lvpecl 100 135 150 100 135 150 100 135 150 ps pcml 80 110 135 80 110 135 80 110 135 ps output t fall lvds 80 110 120 80 110 120 80 110 120 ps hypertransport 110 170 200 110 170 200 110 170 200 ps lvpecl 100 135 160 100 135 160 100 135 160 ps pcml 110 145 175 110 145 175 110 145 175 ps t duty lvds (j = 2 through10) only 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 % lvds (j =1) and lvpecl, pcml, hypertransport technology 45 50 55 45 50 55 45 50 55 % t lock all 100 100 100 s table 4?126. high-speed i/o s pecifications for wire-b ond packages (part 2 of 2) symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max 4?94 altera corporation stratix device handbook, volume 1 july 2005 pll specifications pll specifications tables 4?127 through 4?129 describe the stratix device enhanced pll specifications. table 4?127. enhanced pll specifications for -5 speed grades (part 1 of 2) symbol parameter min typ max unit f in input clock frequency 3 (1) , (2) 684 mhz f inpfd input frequency to pfd 3 420 mhz f induty input clock duty cycle 40 60 % f einduty external feedback clock input duty cycle 40 60 % t injitter input clock period jitter 200 (3) ps t einjitter external feedback clock period jitter 200 (3) ps t fcomp external feedback clock compensation time (4) 6ns f out output frequency for internal global or regional clock 0.3 500 mhz f out_ext output frequency for external clock (3) 0.3 526 mhz t outduty duty cycle for external clock output (when set to 50 % ) 45 55 % t jitter period jitter for external clock output (6) 100 ps for >200-mhz outclk 20 mui for <200-mhz outclk ps or mui t config5,6 time required to reconfigure the scan chains for plls 5 and 6 289/f scanclk t config11,12 time required to reconfigure the scan chains for plls 11 and 12 193/f scanclk t scanclk scanclk frequency (5) 22 mhz t dlock time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) (7) 100 s t lock time required to lock from end of device configuration 10 400 s f vco pll internal vco operating range 300 800 (8) mhz t lskew clock skew between two external clock outputs driven by the same counter 50 ps altera corporation 4?95 july 2005 stratix device handbook, volume 1 dc & switching characteristics t skew clock skew between two external clock outputs driven by the different counters with the same settings 75 ps f ss spread spectrum modulation frequency 30 150 khz % spread percentage spread for spread spectrum frequency (10) 0.4 0.5 0.6 % t areset minimum pulse width on areset signal 10 ns t areset_recon fig minimum pulse width on the areset signal when using pll reconfiguration. reset the pll after scandataout goes high. 500 ns table 4?128. enhanced pll specifications for -6 speed grades (part 1 of 2) symbol parameter min typ max unit f in input clock frequency 3 (1) , (2) 650 mhz f inpfd input frequency to pfd 3 420 mhz f induty input clock duty cycle 40 60 % f einduty external feedback clock input duty cycle 40 60 % t injitter input clock period jitter 200 (3) ps t einjitter external feedback clock period jitter 200 (3) ps t fcomp external feedback clock compensation time (4) 6ns f out output frequency for internal global or regional clock 0.3 450 mhz f out_ext output frequency for external clock (3) 0.3 500 mhz t outduty duty cycle for external clock output (when set to 50 % ) 45 55 % t jitter period jitter for external clock output (6) 100 ps for >200-mhz outclk 20 mui for <200-mhz outclk ps or mui t config5,6 time required to reconfigure the scan chains for plls 5 and 6 289/f scanclk t config11,12 time required to reconfigure the scan chains for plls 11 and 12 193/f scanclk table 4?127. enhanced pll specifications for -5 speed grades (part 2 of 2) symbol parameter min typ max unit 4?96 altera corporation stratix device handbook, volume 1 july 2005 pll specifications t scanclk scanclk frequency (5) 22 mhz t dlock time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) (7) (11) (9) 100 s t lock time required to lock from end of device configuration (11) 10 400 s f vco pll internal vco operating range 300 800 (8) mhz t lskew clock skew between two external clock outputs driven by the same counter 50 ps t skew clock skew between two external clock outputs driven by the different counters with the same settings 75 ps f ss spread spectrum modulation frequency 30 150 khz % spread percentage spread for spread spectrum frequency (10) 0.4 0.5 0.6 % t areset minimum pulse width on areset signal 10 ns table 4?129. enhanced pll specifications for -7 speed grade (part 1 of 2) symbol parameter min typ max unit f in input clock frequency 3 (1) , (2) 565 mhz f inpfd input frequency to pfd 3 420 mhz f induty input clock duty cycle 40 60 % f einduty external feedback clock input duty cycle 40 60 % t injitter input clock period jitter 200 (3) ps t einjitter external feedback clock period jitter 200 (3) ps t fcomp external feedback clock compensation time (4) 6ns f out output frequency for internal global or regional clock 0.3 420 mhz f out_ext output frequency for external clock (3) 0.3 434 mhz table 4?128. enhanced pll specifications for -6 speed grades (part 2 of 2) symbol parameter min typ max unit altera corporation 4?97 july 2005 stratix device handbook, volume 1 dc & switching characteristics t outduty duty cycle for external clock output (when set to 50 % ) 45 55 % t jitter period jitter for external clock output (6) 100 ps for >200-mhz outclk 20 mui for <200-mhz outclk ps or mui t config5,6 time required to reconfigure the scan chains for plls 5 and 6 289/f scanclk t config11,12 time required to reconfigure the scan chains for plls 11 and 12 193/f scanclk t scanclk scanclk frequency (5) 22 mhz t dlock time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) (7) (11) (9) 100 s t lock time required to lock from end of device configuration (11) 10 400 s f vco pll internal vco operating range 300 600 (8) mhz t lskew clock skew between two external clock outputs driven by the same counter 50 ps t skew clock skew between two external clock outputs driven by the different counters with the same settings 75 ps f ss spread spectrum modulation frequency 30 150 khz % spread percentage spread for spread spectrum frequency (10) 0.5 0.6 % t areset minimum pulse width on areset signal 10 ns table 4?130. enhanced pll specifications for -8 speed grade (part 1 of 3) symbol parameter min typ max unit f in input clock frequency 3 (1) , (2) 480 mhz f inpfd input frequency to pfd 3 420 mhz f induty input clock duty cycle 40 60 % f einduty external feedback clock input duty cycle 40 60 % t injitter input clock period jitter 200 (3) ps table 4?129. enhanced pll specifications for -7 speed grade (part 2 of 2) symbol parameter min typ max unit 4?98 altera corporation stratix device handbook, volume 1 july 2005 pll specifications t einjitter external feedback clock period jitter 200 (3) ps t fcomp external feedback clock compensation time (4) 6ns f out output frequency for internal global or regional clock 0.3 357 mhz f out_ext output frequency for external clock (3) 0.3 369 mhz t outduty duty cycle for external clock output (when set to 50 % ) 45 55 % t jitter period jitter for external clock output (6) 100 ps for >200-mhz outclk 20 mui for <200-mhz outclk ps or mui t config5,6 time required to reconfigure the scan chains for plls 5 and 6 289/f scanclk t config11,12 time required to reconfigure the scan chains for plls 11 and 12 193/f scanclk t scanclk scanclk frequency (5) 22 mhz t dlock time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) (7) (11) (9) 100 s t lock time required to lock from end of device configuration (11) 10 400 s f vco pll internal vco operating range 300 600 (8) mhz table 4?130. enhanced pll specifications for -8 speed grade (part 2 of 3) symbol parameter min typ max unit altera corporation 4?99 july 2005 stratix device handbook, volume 1 dc & switching characteristics t lskew clock skew between two external clock outputs driven by the same counter 50 ps t skew clock skew between two external clock outputs driven by the different counters with the same settings 75 ps f ss spread spectrum modulation frequency 30 150 khz % spread percentage spread for spread spectrum frequency (10) 0.5 0.6 % t areset minimum pulse width on areset signal 10 ns notes to tables 4?127 through 4?130 : (1) the minimum input clock frequency to the pfd (f in / n ) must be at least 3 mhz for st ratix device enhanced plls. (2) use this equation (f out = f in * ml ( n post-scale counter)) in co njunction with the specified f inpfd and f vco ranges to determine the al lowed pll settings. (3) see ?maximum input & output clock rates? on page 4?76 . (4) t fcomp can also equal 50 % of the input clock period multiplied by the pre-scale divider n (whichever is less). (5) this parameter is timing analyzed by the quartus ii software because the scanclk and scandata ports can be driven by the logic array. (6) actual jitter performance may vary based on the system configuration. (7) total required time to reconfigure and lock is equal to t dlock + t config . if only post-scale co unters and delays are changed, then t dlock is equal to 0. (8) when using the spread-spectrum feature, the min imum vco frequency is 500 mhz. the maximum vco frequency is determined by the speed grade selected. (9) lock time is a function of pll configuration and may be significantly faster dependin g on bandwidth settings or feedback counter change increment. (10) exact, user-controllable valu e depends on the pll settings. (11) the lock circuit on stratix plls does not work for industrial devices below -20c unless the pfd frequency > 200 mhz. see the stratix fpga errata sheet for more information on the pll. table 4?130. enhanced pll specifications for -8 speed grade (part 3 of 3) symbol parameter min typ max unit 4?100 altera corporation stratix device handbook, volume 1 july 2005 pll specifications tables 4?131 through 4?133 describe the stratix device fast pll specifications. table 4?131. fast pll specifications for -5 & -6 speed grade devices symbol parameter min max unit f in clkin frequency (1) , (2) , (3) 10 717 mhz f inpfd input frequency to pfd 10 500 mhz f out output frequency for internal global or regional clock (3) 9.375 420 mhz f out_diffio output frequency for external clock driven out on a differential i/o data channel (2) (5) (5) f vco vco operating frequency 300 1,000 mhz t induty clkin duty cycle 40 60 % t injitter period jitter for clkin pin 200 ps t duty duty cycle for dffio 1 clkout pin (6) 45 55 % t jitter period jitter for diffio clock out (6) (5) ps t lock time required for pll to acquire lock 10 100 s m multiplication factors for m counter (6) 1 32 integer l 0, l 1, g 0 multiplication factors for l 0, l 1, and g 0 counter (7) , (8) 1 32 integer t areset minimum pulse width on areset signal 10 ns table 4?132. fast pll specifications for -7 speed grades (part 1 of 2) symbol parameter min max unit f in clkin frequency (1) , (3) 10 640 mhz f inpfd input frequency to pfd 10 500 mhz f out output frequency for internal global or regional clock (4) 9.375 420 mhz f out_diffio output frequency for external clock driven out on a differential i/o data channel (5) (5) mhz f vco vco operating frequency 300 700 mhz t induty clkin duty cycle 40 60 % t injitter period jitter for clkin pin 200 ps t duty duty cycle for dffio 1 clkout pin (6) 45 55 % altera corporation 4?101 july 2005 stratix device handbook, volume 1 dc & switching characteristics t jitter period jitter for diffio clock out (6) (5) ps t lock time required for pll to acquire lock 10 100 s m multiplication factors for m counter (7) 1 32 integer l 0, l 1, g 0 multiplication factors for l 0, l 1, and g 0 counter (7) , (8) 1 32 integer t areset minimum pulse width on areset signal 10 ns table 4?133. fast pll specifications for -8 speed grades (part 1 of 2) symbol parameter min max unit f in clkin frequency (1) , (3) 10 460 mhz f inpfd input frequency to pfd 10 500 mhz f out output frequency for internal global or regional clock (4) 9.375 420 mhz f out_diffio output frequency for external clock driven out on a differential i/o data channel (5) (5) mhz f vco vco operating frequency 300 700 mhz t induty clkin duty cycle 40 60 % t injitter period jitter for clkin pin 200 ps t duty duty cycle for dffio 1 clkout pin (6) 45 55 % t jitter period jitter for diffio clock out (6) (5) ps t lock time required for pll to acquire lock 10 100 s m multiplication factors for m counter (7) 1 32 integer l 0, l 1, g 0 multiplication factors for l 0, l 1, and g 0 counter (7) , (8) 1 32 integer table 4?132. fast pll specifications for -7 speed grades (part 2 of 2) symbol parameter min max unit 4?102 altera corporation stratix device handbook, volume 1 july 2005 dll jitter dll jitter table 4?134 reports the jitter for the dll in the dqs phase shift reference circuit. f for more information on dll jitter, see the ddr sram section in the stratix architecture chapter of the stratix device handbook, volume 1 . t areset minimum pulse width on areset signal 10 ns notes to tables 4?131 through 4?133 : (1) see ?maximum input & output clock rates? on page 4?76 . (2) plls 7, 8, 9, and 10 in the ep1s80 device support up to 717-mhz input and output. (3) use this equation (f out = f in * ml ( n post-scale counter)) in conjunction with the specified f inpfd and f vco ranges to determine the allowed pll settings. (4) when using the serdes, high-speed differential i/o mode supports a maximum output frequency of 210 mhz to the global or regional clocks (that is, the maximum data rate 840 mbps divided by the smallest serdes j factor of 4). (5) refer to the section ?high-speed i/o specification? on page 4?87 for more information. (6) this parameter is for high-spe ed differential i/o mode only. (7) these counters have a maximum of 32 if programmed for 50/50 duty cycle. otherwise, they have a maximum of 16. (8) high-speed differential i/o mode supports w = 1 to 16 and j = 4, 7, 8, or 10. table 4?133. fast pll specifications for -8 speed grades (part 2 of 2) symbol parameter min max unit table 4?134. dll jitter for dqs ph ase shift reference circuit frequency (mhz) dll jitter (ps) 197 to 200 100 160 to 196 300 100 to 159 500 altera corporation 5?1 september 2004 5. reference & ordering information software stratix ? devices are supported by the altera ? quartus ? ii design software, which provides a comprehe nsive environment for system-on-a- programmable-chip (sopc) design. the quartus ii software includes hdl and schematic design entry, comp ilation and logic synthesis, full simulation and advanced ti ming analysis, signaltap ? ii logic analyzer, and device configuration. see the design software selector guide for more details on the quartus ii software features. the quartus ii software supports the windows xp/2000/nt/98, sun solaris, linux red hat v7.1 and hp-ux operating systems. it also supports seamless integr ation with industry-leading eda tools through the nativelink ? interface. device pin-outs stratix device pin-outs can be found on the altera web site (www.altera.com). ordering information figure 5?1 describes the ordering codes for stratix devices. for more information on a specif ic package, see the package information for stratix devices chapter. s51005-2.1 5?2 altera corporation stratix device handbook, volume 1 september 2004 ordering information figure 5?1. stratix device pa ckaging ordering information device type package type 5, 6, or 7, with 5 bein g the fastest number of pins for a particular bga or fineline bga packa g e es: b: f: ball- g rid array (bga) fineline bga ep1s: stratix 10 20 25 30 40 60 80 c: i: commercial temperature (t j = 0 ? c to 85 ? c) industrial temperature (t j = -40 ? c to 100 ? c) optional suffix family signature operating temperature speed grade pin count en g ineerin g sample 7 ep1s 8 0c 150 8 fes indicates specific device options or shipment method. altera corporation index?1 index a accumulator 2?63 adder/output blocks 2?61 adder/subtractor 2?63 accumulator 2?63 agp 1x specifications 4?13 agp 2x specifications 4?13 architecture 2?1 36 x 36 multiply mode 2?66 addnsub signal 2?8 block diagram 2?2 bus hold 2?121 byte alignment 2?140 carry-select chain 2?11 clear & preset logic control 2?13 combined resources 2?78 dedicated circuitry 2?137 device resources 2?3 device routing scheme 2?20 digital signal pr ocessing block 2?52 direct link connection 2?5 dynamic arithmetic mode 2?10 in le 2?11 four-multipliers adder mode 2?68 functional description 2?1 lab interconnects 2?4 logic array blocks 2?3 structure 2?4 le operating modes 2?8 logic elements 2?6 modes of operation 2?64 multiplier size & configurations per dsp block 2?70 multiply-accumulator mode 2?67 multitrack interconnect 2?14 normal mode 2?9 in le 2?9 open-drain output 2?120 power sequencing & hot socketing 2?140 programmable drive strength 2?119 programmable pull-up resistor 2?122 simple multiplier mode 2?64 single-port mode 2?51 slew-rate control 2?120 two-multipliers adder mode 2?67 adder mode implementing complex multiply 2?68 c class i specifications 4?11 , 4?12 class ii specifications 4?11 , 4?12 , 4?13 clocks clock feedback 2?96 clock multiplication & division 2?88 , 2?101 clock switchover 2?88 delay 2?97 ep1s10, ep1s20 & ep1s25 device i/o clock groups 2?80 ep1s25, ep1s20 & ep1s 10 device fast clock pin connections to fast regional clocks 2?77 ep1s30 device fast re gional clock pin con- nections to fast regional clocks 2?78 ep1s30, ep1s40, ep1s60, ep1s80 device i/o clock groups 2?81 external clock inputs 2?102 outputs 2?92 , 2?103 outputs for enhanced plls 11 & 12 2?95 outputs for plls 5 & 6 2?93 fast regional clock external i/o timing parameters 4?34 fast regional clock network 2?76 index?2 altera corporation stratix device handbook, volume 1 global & hierarchical clocking 2?73 global & regional clock connections from side pins & fast pll outputs 2?85 from top clock pins & enhanced pll outputs 2?86 global clock external i/o timing parameters 4?35 global clock network 2?74 global clocking 2?75 independent clock mode 2?44 input/output clock mode 2?46 simple dual-port mode 2?48 true dual-port mode 2?47 maximum input & output clock rates 4?76 maximum input clock rate for clk (0, 2, 9, 11) pins in flip-chip packages 4?77 wire-bond packages 4?79 (1, 3, 8, 10) pins in flip-chip packages 4?78 wire-bond packages 4?80 (7..4) & clk(15..12) pins in flip-chip packages 4?76 wire-bond packages 4?78 maximum output clock rate for pll (1, 2, 3, 4) pins in flip-chip packages 4?83 wire-bond packages 4?85 (5, 6, 11, 12) pins in flip-chip packages 4?81 wire-bond packages 4?84 phase & delay shifting 2?96 phase delay 2?96 pll clock networks 2?73 read/write clock mode 2?49 in simple dual-port mode 2?50 regional clock 2?75 external i/o timing parameters 4?34 regional clock bus 2?79 regional clock network 2?75 spread-spectrum clocking 2?98 configuration 3?5 32-bit idcode 3?3 and testing 3?1 data sources for configuration 3?7 local update mode 3?12 local update transition diagram 3?12 operating modes 3?5 partial reconfiguration 3?7 remote update 3?8 remote update transition diagram 3?11 schemes 3?7 signaltap ii embedded logic analyzer 3?5 stratix fpgas with jrunner 3?7 control signals 2?104 d dc switching absolute maximum ratings 4?1 bus hold parameters 4?16 capacitance 4?17 dc & switching characteristics 4?1 external timing parameters 4?33 operating conditions 4?1 performance 4?20 power consumption 4?17 recommended operating conditions 4?1 ddr double-data rate i/o pins 2?111 device features ep1s10, ep1s20, ep1s25, ep1s30, 1?3 ep1s40, ep1s60, ep1s80, 1?3 altera corporation index?3 stratix device handbook, volume 1 differential hstl specifications 4?15 dsp block diagram configuration for 18 x 18-bit 2?55 for 9 x 9-bit 2?56 block interconnect interface 2?71 block interface 2?70 block signal sources & destinations 2?73 blocks arranged in columns 2?53 in stratix devices 2?54 input register modes 2?60 input registers 2?58 multiplier 2?60 block 2?57 signed representation 2?60 sub-block 2?57 sub-blocks using input shift register connections 2?59 pipeline/post mu ltiply register 2?61 e ep1s10 devices column pin fast regional clock external i/o timing parameters 4?36 global clock external i/o timing parameters 4?37 regional clock ex ternal i/o timing parameters 4?36 row pin fast regional clock external i/o timing parameters 4?37 global clock external i/o timing parameters 4?38 regional clock ex ternal i/o timing parameters 4?38 ep1s20 devices column pin fast regional clock external i/o timing parameters 4?39 global clock external i/o timing parameters 4?40 regional clock ex ternal i/o timing parameters 4?39 row pin fast regional clock external i/o timing parameters 4?40 global clock exte rnal i/o timing parameters 4?41 regional clock external i/o timing parameters 4?41 ep1s25 devices column pin fast regional clock external i/o timing parameters 4?42 global clock exte rnal i/o timing parameters 4?43 regional clock external i/o timing parameters 4?42 row pin fast regional clock external i/o timing parameters 4?43 global clock exte rnal i/o timing parameters 4?44 regional clock external i/o timing parameters 4?44 ep1s30 devices column pin fast regional clock external i/o timing parameters 4?45 global clock exte rnal i/o timing parameters 4?45 regional clock external i/o timing parameters 4?45 row pin fast regional clock external i/o timing parameters 4?46 global clock exte rnal i/o timing parameters 4?47 regional clock external i/o timing parameters 4?47 ep1s40 devices column pin fast regional clock external i/o timing parameters 4?48 global clock exte rnal i/o timing parameters 4?49 regional clock external i/o timing parameters 4?48 row pin index?4 altera corporation stratix device handbook, volume 1 fast regional clock external i/o timing parameters 4?49 global clock external i/o timing parameters 4?50 regional clock ex ternal i/o timing parameters 4?50 ep1s60 devices column pin fast regional clock external i/o timing parameters 4?51 global clock external i/o timing parameters 4?52 regional clock ex ternal i/o timing parameters 4?51 m-ram interface locations 2?38 row pin fast regional clock external i/o timing parameters 4?52 global clock external i/o timing parameters 4?53 regional clock ex ternal i/o timing parameters 4?53 ep1s80 devices column pin fast regional clock external i/o timing parameters 4?54 global clock external i/o timing parameters 4?55 regional clock ex ternal i/o timing parameters 4?54 global clock external i/o timing parameters 4?56 row pin fast regional clock external i/o timing parameters 4?55 regional clock ex ternal i/o timing parameters 4?56 h hstl class i specifications 4?14 , 4?15 class ii specifications 4?14 , 4?15 i i/o standards 1.5-v 4?14 , 4?15 i/o specifications 4?4 1.8-v i/o specifications 4?4 2.5-v i/o specifications 4?3 3.3-v 4?13 lvds i/o specifications 4?6 pci specifications 4?9 pcml specifications 4?8 advanced i/o standard support 2?122 column i/o block connection to the interconnect 2?107 column pin input delay adders 4?66 control signal selection per ioe 2?109 ctt i/o specifications 4?16 differential lvds input on-chip termination 2?128 external i/o delay parameters 4?66 gtl+ i/o specifications 4?10 high-speed differential i/o support 2?130 hypertransport technology specifications 4?9 i/o banks 2?125 i/o structure 2?104 i/o support by bank 2?126 ioe structure 2?105 lvcmos specifications 4?3 lvds performance on fast pll input 2?103 lvpecl specifications 4?8 lvttl specifications 4?3 multivolt i/o interface 2?129 multivolt i/o support 2?130 output delay adders for fast slew rate on column pins 4?68 output delay adders for fast slew rate on row pins 4?69 output delay adders for slow slew rate on column pins 4?70 package options & i/o pin counts 1?4 receiver input waveforms for differential altera corporation index?5 stratix device handbook, volume 1 i/o standards 4?5 row i/o block connection to the interconnect 2?106 row pin input delay adders 4?67 signal path through the i/o block 2?108 sstl-18 4?11 sstl-2 4?12 sstl-3 4?12 , 4?13 stratix ioe in bidirectional i/o configuration 2?110 supported i/o standards 2?123 transmitter output waveforms for differ- ential i/o standards 4?6 interconnect c4 connections 2?18 dsp block interfac e to interconnect 2?72 left-facing m-ram to interconnect interface 2?40 lut chain register chain interconnects 2?17 m-ram column unit interface to interconnect 2?42 row unit interface to interconnect 2?41 r4 connections 2?15 ioe internal timing microparameters 4?29 j jtag boundary-scan register length 3?3 support 3?1 stratix jtag instructions 3?2 waveforms 3?4 l lab control signals 2?5 wide control signals 2?6 lut chain & register chain 2?8 m memory architecture byte enable for m4k ram block 2?32 byte enable for m-ram block 2?35 external ram interfacing 2?115 m4k block internal timing microparameter descriptions 4?24 microparameters 4?31 ram block 2?30 configurations (simple dual- port) 2?31 configurations (true dual- port) 2?31 control signals 2?33 lab row interface 2?33 m512 block internal timing microparameter descriptions 4?24 microparameters 4?30 ram block architecture 2?27 configurations (simple dual-port ram) 2?27 control signals 2?29 lab row interface 2?30 memory block size 2?26 memory modes 2?21 m-ram block 2?34 configurations (simple dual- port) 2?34 configurations (true dual- port) 2?35 block control signals 2?37 block internal timing microparameter descriptions 4?25 combined byte selection for x144 index?6 altera corporation stratix device handbook, volume 1 mode 2?36 row & column interface unit signals 2?43 parity bit support 2?24 shift register memory configuration 2?26 support 2?25 simple dual-port & single-port memory configurations 2?23 stratix ioe in ddr input i/o configuration 2?112 stratix ioe in ddr output i/o configuration 2?114 trimatrix memory 2?21 true dual-port memory configuration 2?22 o ordering information 5?1 device pin-outs 5?1 packaging ordering information 5?2 reference & ordering information 5?1 output registers 2?64 output selection multiplexer 2?64 p packaging bga package sizes 1?4 device speed grades 1?5 fineline bga package sizes 1?5 pci-x 1.0 specifications 4?10 phase shifting 2?103 pll advanced clear & enable control 2?98 dynamically programmable counters & de- lays in stratix device enhanced plls 2?91 enhanced fast plls 2?81 fast pll 2?100 channel layout ep1s10, ep1s20 or ep1s25 devices 2?138 channel layout ep1s30 to ep1s80 devices 2?139 port i/o standards 2?102 i/o standards supported for enhanced pll pins 2?94 lock detect & programmable gated locked 2?98 pll locations 2?84 programmable bandwidth 2?91 programmable delay chain 2?111 programmable duty cycle 2?98 reconfiguration 2?90 t testing temperature sensing diode 3?13 electrical characteristics 3?14 external 3?14 temperature vs. temperature-sensing diode voltage 3?15 timing dsp block internal timing microparameter descriptions 4?23 microparameters 4?29 dual-port ram timing microparameter waveform 4?27 external timing in stratix devices 4?33 high-speed i/o timing 4?87 high-speed timing specifications & terminology 4?87 internal parameters 4?22 ioe internal timing microparameter descriptions 4?22 le internal timing microparameters 4?28 logic elements internal timing microparam- eter descriptions 4?22 model 4?19 pll timing 4?94 preliminary & final 4?19 stratix device timing model status 4?19 stratix jtag timing parameters & values 3?4 trimatrix memory trimatrix memory features 2?21 |
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